[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3e = C:/Microsemi/Libero_v11.5/Designer/lib/modelsim/precompiled/vhdl/proasic3e

syncad_vhdl_lib = C:\Microsemi\Libero_v11.5\Designer/lib/actel/syncad_vhdl_lib

work = work
[vcom]
VHDL93 = 93

NoDebug = 0
Explicit = 1
CheckSynthesis = 0
NoVitalCheck = 1
Optimize_1164 = 1
NoVital = 1
Quiet = 1
Show_source = 1
DisableOpt = 0
ZeroIn = 0
CoverageNoSub = 0
NoCoverage = 1
CoverCells = 0
CoverExcludeDefault = 0
CoverFEC = 1
CoverShortCircuit = 1
CoverOpt = 3
Show_Warning1 = 0
Show_Warning2 = 1
Show_Warning3 = 0
Show_Warning4 = 1
Show_Warning5 = 1
[vsim]
IterationLimit = 1000
VoptFlow = 1
DefaultRadix = hexadecimal
RunLength = 450 us
BreakOnAssertion = 4
IgnoreWarning = 1
IgnoreNote = 1
WLFCompress = 0
WLFDeleteOnQuit = 1
[vlog]
vlog95compat = 0
Vlog01Compat = 0
Svlog = 0
CoverCells = 0
CoverExcludeDefault = 0
CoverFEC = 1
CoverShortCircuit = 1
CoverOpt = 3
OptionFile = ./vlog.opt
Quiet = 0
Show_source = 0
Protect = 0
NoDebug = 0
Hazard = 0
UpCase = 0
DisableOpt = 0
ZeroIn = 0
[Project]
; Warning -- Do not edit the project properties directly.
;            Property names are dynamic in nature and property
;            values have special syntax.  Changing property data directly
;            can result in a corrupt MPF file.  All project properties
;            can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 9
Project_File_0 = ../uCore/uart.vhd
Project_File_P_0 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 cover_branch 0 cover_fsm 0 vhdl_disableopt 0 last_compile 1449571887 folder {Top Level} cover_excludedefault 0 vhdl_vital 1 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vhdl_warn3 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 93
Project_File_1 = ../uCore/bootload.vhd
Project_File_P_1 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 cover_branch 0 cover_fsm 0 vhdl_disableopt 0 last_compile 1449248617 folder {Top Level} cover_excludedefault 0 vhdl_vital 1 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vhdl_warn3 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 93
Project_File_2 = ../uCore/bench.vhd
Project_File_P_2 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 cover_branch 0 cover_fsm 0 vhdl_disableopt 0 last_compile 1449572547 folder {Top Level} cover_excludedefault 0 vhdl_vital 1 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vhdl_warn3 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 93
Project_File_3 = ../uCore/debugger.vhd
Project_File_P_3 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 cover_branch 0 cover_fsm 0 vhdl_disableopt 0 last_compile 1449571614 folder {Top Level} cover_excludedefault 0 vhdl_vital 1 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vhdl_warn3 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 93
Project_File_4 = ../uCore/constants.vhd
Project_File_P_4 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 cover_branch 0 cover_fsm 0 vhdl_disableopt 0 last_compile 1449756210 folder {Top Level} cover_excludedefault 0 vhdl_vital 1 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vhdl_warn3 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 93
Project_File_5 = ../uCore/functions.vhd
Project_File_P_5 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 cover_branch 0 cover_fsm 0 vhdl_disableopt 0 last_compile 1449484269 folder {Top Level} cover_excludedefault 0 vhdl_vital 1 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vhdl_warn3 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 93
Project_File_6 = ../uCore/fpga.vhd
Project_File_P_6 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 cover_branch 0 cover_fsm 0 vhdl_disableopt 0 last_compile 1449756825 folder {Top Level} cover_excludedefault 0 vhdl_vital 1 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vhdl_warn3 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 93
Project_File_7 = ../uCore/uCore.vhd
Project_File_P_7 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1449756949 vhdl_disableopt 0 cover_fsm 0 cover_branch 0 vhdl_vital 1 cover_excludedefault 0 vhdl_warn1 0 vhdl_showsource 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 0 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 cover_expr 0 vhdl_use93 93 cover_stmt 0
Project_File_8 = D:/technik/microcore/uCore_branch/uCore/uCntrl.vhd
Project_File_P_8 = cover_toggle 0 vhdl_novitalcheck 1 file_type vhdl group_id 0 cover_exttoggle 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 cover_cond 0 vhdl_noload 1 vhdl_synth 0 vhdl_enable0In 0 cover_branch 0 cover_fsm 0 vhdl_disableopt 0 last_compile 1449756646 folder {Top Level} cover_excludedefault 0 vhdl_vital 1 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vhdl_warn3 0 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_expr 0 cover_nosub 0 dont_compile 0 cover_stmt 0 vhdl_use93 93
Project_Sim_Count = 1
Project_Sim_0 = simulation
Project_Sim_P_0 = timing default -t ns -sdfnoerror 0 -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {Top Level} +pulse_e {} additional_dus work.bench -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
Project_Folder_Count = 0
Echo_Compile_Output = 1
Save_Compile_Report = 0
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick = 
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick = 
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick = 
PSL_DoubleClick = Edit
PSL_CustomDoubleClick = 
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick = 
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick = 
TCL_DoubleClick = Edit
TCL_CustomDoubleClick = 
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick = 
VCD_DoubleClick = Edit
VCD_CustomDoubleClick = 
SDF_DoubleClick = Edit
SDF_CustomDoubleClick = 
XML_DoubleClick = Edit
XML_CustomDoubleClick = 
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick = 
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick = 
TDB_DoubleClick = Edit
TDB_CustomDoubleClick = 
UPF_DoubleClick = Edit
UPF_CustomDoubleClick = 
PCF_DoubleClick = Edit
PCF_CustomDoubleClick = 
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick = 
VRM_DoubleClick = Edit
VRM_CustomDoubleClick = 
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick = 
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick = 
Project_Major_Version = 10
Project_Minor_Version = 3