###############################################################################
# #
# IAR Assembler V5.30.1.50284/W32 for MSP430 11/May/2012 22:17:13 #
# Copyright 1996-2011 IAR Systems AB. #
# #
# Target option = MSP430 #
# Source file = C:\Dokumente und Einstellungen\All Users\Dokumente\CF430G2553\core430G2553.s43#
# List file = C:\Dokumente und Einstellungen\All Users\Dokumente\CF430G2553\Debug\List\core430G2553.lst#
# Object file = C:\Dokumente und Einstellungen\All Users\Dokumente\CF430G2553\Debug\Obj\core430G2553.r43#
# Command line = C:\Dokumente und Einstellungen\All Users\Dokumente\CF430G2553\core430G2553.s43 #
# -OC:\Dokumente und Einstellungen\All Users\Dokumente\CF430G2553\Debug\Obj\ #
# -s+ -M<> -w+ #
# -LC:\Dokumente und Einstellungen\All Users\Dokumente\CF430G2553\Debug\List\ #
# -cE -i -t8 -xD -D__MSP430G2553__ #
# -IC:\Programme\IAR Systems\Embedded Workbench 6.0 Kickstart\430\INC\ #
# #
###############################################################################
1 000000 ; ----------------------------------------------
------------------------
2 000000 ; CF430G2553 is a Forth based on CamelForth
3 000000 ; for the Texas Instruments MSP430
4 000000 ;
5 000000 ; This program is free software; you can
redistribute it and/or modify
6 000000 ; it under the terms of the GNU General Public
License as published by
7 000000 ; the Free Software Foundation; either version 3
of the License, or
8 000000 ; (at your option) any later version.
9 000000 ;
10 000000 ; This program is distributed in the hope that
it will be useful,
11 000000 ; but WITHOUT ANY WARRANTY; without even the
implied warranty of
12 000000 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the
13 000000 ; GNU General Public License for more details.
14 000000 ;
15 000000 ; You should have received a copy of the GNU
General Public License
16 000000 ; along with this program. If not, see
.
17 000000 ;
18 000000 ; See LICENSE TERMS in Brads file readme.txt as
well.
19 000000
20 000000 ; ----------------------------------------------
------------------------
21 000000 ; core430.s43 - Machine Language Primitives -
MSP430G2553
22 000000 ; ----------------------------------------------
------------------------
23 000000
24 000000 ; Revision History
25 000000 ; 1 mar 09 bjr - changed Flash write and erase
primitives to correctly
26 000000 ; write RAM outside Info Flash and Main
Flash address limits.
27 000000
28 000000 #include "msp430.h" ;
#define controlled include file
1 000000 /***********************************************
********************
2 000000 *
*
3 000000 * This file is a generic include file controlled
by *
4 000000 * compiler/assembler IDE generated defines
*
5 000000 *
*
6 000000 ************************************************
*******************/
7 000000
8 000000 #ifndef __msp430
9 000000 #define __msp430
10 000000
11 000000 #ifndef _SYSTEM_BUILD
12 000000 #pragma system_include
13 000000 #endif
14 000000
15 000000 #if defined (__MSP430C111__)
16 000000 #include "msp430c111.h"
18 000000 #elif defined (__MSP430C1111__)
19 000000 #include "msp430c1111.h"
21 000000 #elif defined (__MSP430C112__)
22 000000 #include "msp430c112.h"
24 000000 #elif defined (__MSP430C1121__)
25 000000 #include "msp430c1121.h"
27 000000 #elif defined (__MSP430C1331__)
28 000000 #include "msp430c1331.h"
30 000000 #elif defined (__MSP430C1351__)
31 000000 #include "msp430c1351.h"
33 000000 #elif defined (__MSP430C311S__)
34 000000 #include "msp430c311s.h"
36 000000 #elif defined (__MSP430C312__)
37 000000 #include "msp430c312.h"
39 000000 #elif defined (__MSP430C313__)
40 000000 #include "msp430c313.h"
42 000000 #elif defined (__MSP430C314__)
43 000000 #include "msp430c314.h"
45 000000 #elif defined (__MSP430C315__)
46 000000 #include "msp430c315.h"
48 000000 #elif defined (__MSP430C323__)
49 000000 #include "msp430c323.h"
51 000000 #elif defined (__MSP430C325__)
52 000000 #include "msp430c325.h"
54 000000 #elif defined (__MSP430C336__)
55 000000 #include "msp430c336.h"
57 000000 #elif defined (__MSP430C337__)
58 000000 #include "msp430c337.h"
60 000000 #elif defined (__MSP430C412__)
61 000000 #include "msp430c412.h"
63 000000 #elif defined (__MSP430C413__)
64 000000 #include "msp430c413.h"
66 000000 #elif defined (__MSP430CG4616__)
67 000000 #include "msp430cg4616.h"
69 000000 #elif defined (__MSP430CG4617__)
70 000000 #include "msp430cg4617.h"
72 000000 #elif defined (__MSP430CG4618__)
73 000000 #include "msp430cg4618.h"
75 000000 #elif defined (__MSP430CG4619__)
76 000000 #include "msp430cg4619.h"
78 000000 #elif defined (__MSP430E112__)
79 000000 #include "msp430e112.h"
81 000000 #elif defined (__MSP430E313__)
82 000000 #include "msp430e313.h"
84 000000 #elif defined (__MSP430E315__)
85 000000 #include "msp430e315.h"
87 000000 #elif defined (__MSP430E325__)
88 000000 #include "msp430e325.h"
90 000000 #elif defined (__MSP430E337__)
91 000000 #include "msp430e337.h"
93 000000 #elif defined (__MSP430F110__)
94 000000 #include "msp430f110.h"
96 000000 #elif defined (__MSP430F1101__)
97 000000 #include "msp430f1101.h"
99 000000 #elif defined (__MSP430F1101A__)
100 000000 #include "msp430f1101a.h"
102 000000 #elif defined (__MSP430F1111__)
103 000000 #include "msp430f1111.h"
105 000000 #elif defined (__MSP430F1111A__)
106 000000 #include "msp430f1111a.h"
108 000000 #elif defined (__MSP430F112__)
109 000000 #include "msp430f112.h"
111 000000 #elif defined (__MSP430F1121__)
112 000000 #include "msp430f1121.h"
114 000000 #elif defined (__MSP430F1121A__)
115 000000 #include "msp430f1121a.h"
117 000000 #elif defined (__MSP430F1122__)
118 000000 #include "msp430f1122.h"
120 000000 #elif defined (__MSP430F1132__)
121 000000 #include "msp430f1132.h"
123 000000 #elif defined (__MSP430F122__)
124 000000 #include "msp430f122.h"
126 000000 #elif defined (__MSP430F1222__)
127 000000 #include "msp430f1222.h"
129 000000 #elif defined (__MSP430F123__)
130 000000 #include "msp430f123.h"
132 000000 #elif defined (__MSP430F1232__)
133 000000 #include "msp430f1232.h"
135 000000 #elif defined (__MSP430F133__)
136 000000 #include "msp430f133.h"
138 000000 #elif defined (__MSP430F135__)
139 000000 #include "msp430f135.h"
141 000000 #elif defined (__MSP430F147__)
142 000000 #include "msp430f147.h"
144 000000 #elif defined (__MSP430F148__)
145 000000 #include "msp430f148.h"
147 000000 #elif defined (__MSP430F149__)
148 000000 #include "msp430f149.h"
150 000000 #elif defined (__MSP430F1471__)
151 000000 #include "msp430f1471.h"
153 000000 #elif defined (__MSP430F1481__)
154 000000 #include "msp430f1481.h"
156 000000 #elif defined (__MSP430F1491__)
157 000000 #include "msp430f1491.h"
159 000000 #elif defined (__MSP430F155__)
160 000000 #include "msp430f155.h"
162 000000 #elif defined (__MSP430F156__)
163 000000 #include "msp430f156.h"
165 000000 #elif defined (__MSP430F157__)
166 000000 #include "msp430f157.h"
168 000000 #elif defined (__MSP430F167__)
169 000000 #include "msp430f167.h"
171 000000 #elif defined (__MSP430F168__)
172 000000 #include "msp430f168.h"
174 000000 #elif defined (__MSP430F169__)
175 000000 #include "msp430f169.h"
177 000000 #elif defined (__MSP430F1610__)
178 000000 #include "msp430f1610.h"
180 000000 #elif defined (__MSP430F1611__)
181 000000 #include "msp430f1611.h"
183 000000 #elif defined (__MSP430F1612__)
184 000000 #include "msp430f1612.h"
186 000000 #elif defined (__MSP430F2001__)
187 000000 #include "msp430f2001.h"
189 000000 #elif defined (__MSP430F2011__)
190 000000 #include "msp430f2011.h"
192 000000 #elif defined (__MSP430F2002__)
193 000000 #include "msp430f2002.h"
195 000000 #elif defined (__MSP430F2012__)
196 000000 #include "msp430f2012.h"
198 000000 #elif defined (__MSP430F2003__)
199 000000 #include "msp430f2003.h"
201 000000 #elif defined (__MSP430F2013__)
202 000000 #include "msp430f2013.h"
204 000000 #elif defined (__MSP430F2101__)
205 000000 #include "msp430f2101.h"
207 000000 #elif defined (__MSP430F2111__)
208 000000 #include "msp430f2111.h"
210 000000 #elif defined (__MSP430F2121__)
211 000000 #include "msp430f2121.h"
213 000000 #elif defined (__MSP430F2131__)
214 000000 #include "msp430f2131.h"
216 000000 #elif defined (__MSP430F2112__)
217 000000 #include "msp430f2112.h"
219 000000 #elif defined (__MSP430F2122__)
220 000000 #include "msp430f2122.h"
222 000000 #elif defined (__MSP430F2132__)
223 000000 #include "msp430f2132.h"
225 000000 #elif defined (__MSP430F2232__)
226 000000 #include "msp430f2232.h"
228 000000 #elif defined (__MSP430F2252__)
229 000000 #include "msp430f2252.h"
231 000000 #elif defined (__MSP430F2272__)
232 000000 #include "msp430f2272.h"
234 000000 #elif defined (__MSP430F2234__)
235 000000 #include "msp430f2234.h"
237 000000 #elif defined (__MSP430F2254__)
238 000000 #include "msp430f2254.h"
240 000000 #elif defined (__MSP430F2274__)
241 000000 #include "msp430f2274.h"
243 000000 #elif defined (__MSP430F2330__)
244 000000 #include "msp430f2330.h"
246 000000 #elif defined (__MSP430F2350__)
247 000000 #include "msp430f2350.h"
249 000000 #elif defined (__MSP430F2370__)
250 000000 #include "msp430f2370.h"
252 000000 #elif defined (__MSP430F233__)
253 000000 #include "msp430f233.h"
255 000000 #elif defined (__MSP430F235__)
256 000000 #include "msp430f235.h"
258 000000 #elif defined (__MSP430F247__)
259 000000 #include "msp430f247.h"
261 000000 #elif defined (__MSP430F248__)
262 000000 #include "msp430f248.h"
264 000000 #elif defined (__MSP430F249__)
265 000000 #include "msp430f249.h"
267 000000 #elif defined (__MSP430F2410__)
268 000000 #include "msp430f2410.h"
270 000000 #elif defined (__MSP430F2471__)
271 000000 #include "msp430f2471.h"
273 000000 #elif defined (__MSP430F2481__)
274 000000 #include "msp430f2481.h"
276 000000 #elif defined (__MSP430F2491__)
277 000000 #include "msp430f2491.h"
279 000000 #elif defined (__MSP430F2416__)
280 000000 #include "msp430f2416.h"
282 000000 #elif defined (__MSP430F2417__)
283 000000 #include "msp430f2417.h"
285 000000 #elif defined (__MSP430F2418__)
286 000000 #include "msp430f2418.h"
288 000000 #elif defined (__MSP430F2419__)
289 000000 #include "msp430f2419.h"
291 000000 #elif defined (__MSP430F2616__)
292 000000 #include "msp430f2616.h"
294 000000 #elif defined (__MSP430F2617__)
295 000000 #include "msp430f2617.h"
297 000000 #elif defined (__MSP430F2618__)
298 000000 #include "msp430f2618.h"
300 000000 #elif defined (__MSP430F2619__)
301 000000 #include "msp430f2619.h"
303 000000 #elif defined (__MSP430F412__)
304 000000 #include "msp430f412.h"
306 000000 #elif defined (__MSP430F413__)
307 000000 #include "msp430f413.h"
309 000000 #elif defined (__MSP430F415__)
310 000000 #include "msp430f415.h"
312 000000 #elif defined (__MSP430F417__)
313 000000 #include "msp430f417.h"
315 000000 #elif defined (__MSP430F4132__)
316 000000 #include "msp430f4132.h"
318 000000 #elif defined (__MSP430F4152__)
319 000000 #include "msp430f4152.h"
321 000000 #elif defined (__MSP430F423__)
322 000000 #include "msp430f423.h"
324 000000 #elif defined (__MSP430F425__)
325 000000 #include "msp430f425.h"
327 000000 #elif defined (__MSP430F427__)
328 000000 #include "msp430f427.h"
330 000000 #elif defined (__MSP430F423A__)
331 000000 #include "msp430f423a.h"
333 000000 #elif defined (__MSP430F425A__)
334 000000 #include "msp430f425a.h"
336 000000 #elif defined (__MSP430F427A__)
337 000000 #include "msp430f427a.h"
339 000000 #elif defined (__MSP430F435__)
340 000000 #include "msp430f435.h"
342 000000 #elif defined (__MSP430F436__)
343 000000 #include "msp430f436.h"
345 000000 #elif defined (__MSP430F437__)
346 000000 #include "msp430f437.h"
348 000000 #elif defined (__MSP430F4351__)
349 000000 #include "msp430f4351.h"
351 000000 #elif defined (__MSP430F4361__)
352 000000 #include "msp430f4361.h"
354 000000 #elif defined (__MSP430F4371__)
355 000000 #include "msp430f4371.h"
357 000000 #elif defined (__MSP430F4481__)
358 000000 #include "msp430f4481.h"
360 000000 #elif defined (__MSP430F4491__)
361 000000 #include "msp430f4491.h"
363 000000 #elif defined (__MSP430F447__)
364 000000 #include "msp430f447.h"
366 000000 #elif defined (__MSP430F448__)
367 000000 #include "msp430f448.h"
369 000000 #elif defined (__MSP430F449__)
370 000000 #include "msp430f449.h"
372 000000 #elif defined (__MSP430FE423__)
373 000000 #include "msp430fe423.h"
375 000000 #elif defined (__MSP430FE425__)
376 000000 #include "msp430fe425.h"
378 000000 #elif defined (__MSP430FE427__)
379 000000 #include "msp430fe427.h"
381 000000 #elif defined (__MSP430FE423A__)
382 000000 #include "msp430fe423a.h"
384 000000 #elif defined (__MSP430FE425A__)
385 000000 #include "msp430fe425a.h"
387 000000 #elif defined (__MSP430FE427A__)
388 000000 #include "msp430fe427a.h"
390 000000 #elif defined (__MSP430FE4232__)
391 000000 #include "msp430fe4232.h"
393 000000 #elif defined (__MSP430FE4242__)
394 000000 #include "msp430fe4242.h"
396 000000 #elif defined (__MSP430FE4252__)
397 000000 #include "msp430fe4252.h"
399 000000 #elif defined (__MSP430FE4272__)
400 000000 #include "msp430fe4272.h"
402 000000 #elif defined (__MSP430F4783__)
403 000000 #include "msp430f4783.h"
405 000000 #elif defined (__MSP430F4793__)
406 000000 #include "msp430f4793.h"
408 000000 #elif defined (__MSP430F4784__)
409 000000 #include "msp430f4784.h"
411 000000 #elif defined (__MSP430F4794__)
412 000000 #include "msp430f4794.h"
414 000000 #elif defined (__MSP430F47126__)
415 000000 #include "msp430f47126.h"
417 000000 #elif defined (__MSP430F47127__)
418 000000 #include "msp430f47127.h"
420 000000 #elif defined (__MSP430F47163__)
421 000000 #include "msp430f47163.h"
423 000000 #elif defined (__MSP430F47173__)
424 000000 #include "msp430f47173.h"
426 000000 #elif defined (__MSP430F47183__)
427 000000 #include "msp430f47183.h"
429 000000 #elif defined (__MSP430F47193__)
430 000000 #include "msp430f47193.h"
432 000000 #elif defined (__MSP430F47166__)
433 000000 #include "msp430f47166.h"
435 000000 #elif defined (__MSP430F47176__)
436 000000 #include "msp430f47176.h"
438 000000 #elif defined (__MSP430F47186__)
439 000000 #include "msp430f47186.h"
441 000000 #elif defined (__MSP430F47196__)
442 000000 #include "msp430f47196.h"
444 000000 #elif defined (__MSP430F47167__)
445 000000 #include "msp430f47167.h"
447 000000 #elif defined (__MSP430F47177__)
448 000000 #include "msp430f47177.h"
450 000000 #elif defined (__MSP430F47187__)
451 000000 #include "msp430f47187.h"
453 000000 #elif defined (__MSP430F47197__)
454 000000 #include "msp430f47197.h"
456 000000 #elif defined (__MSP430F4250__)
457 000000 #include "msp430f4250.h"
459 000000 #elif defined (__MSP430F4260__)
460 000000 #include "msp430f4260.h"
462 000000 #elif defined (__MSP430F4270__)
463 000000 #include "msp430f4270.h"
465 000000 #elif defined (__MSP430FG4250__)
466 000000 #include "msp430fg4250.h"
468 000000 #elif defined (__MSP430FG4260__)
469 000000 #include "msp430fg4260.h"
471 000000 #elif defined (__MSP430FG4270__)
472 000000 #include "msp430fg4270.h"
474 000000 #elif defined (__MSP430FW423__)
475 000000 #include "msp430fw423.h"
477 000000 #elif defined (__MSP430FW425__)
478 000000 #include "msp430fw425.h"
480 000000 #elif defined (__MSP430FW427__)
481 000000 #include "msp430fw427.h"
483 000000 #elif defined (__MSP430FW428__)
484 000000 #include "msp430fw428.h"
486 000000 #elif defined (__MSP430FW429__)
487 000000 #include "msp430fw429.h"
489 000000 #elif defined (__MSP430FG437__)
490 000000 #include "msp430fg437.h"
492 000000 #elif defined (__MSP430FG438__)
493 000000 #include "msp430fg438.h"
495 000000 #elif defined (__MSP430FG439__)
496 000000 #include "msp430fg439.h"
498 000000 #elif defined (__MSP430F438__)
499 000000 #include "msp430f438.h"
501 000000 #elif defined (__MSP430F439__)
502 000000 #include "msp430f439.h"
504 000000 #elif defined (__MSP430F477__)
505 000000 #include "msp430f477.h"
507 000000 #elif defined (__MSP430F478__)
508 000000 #include "msp430f478.h"
510 000000 #elif defined (__MSP430F479__)
511 000000 #include "msp430f479.h"
513 000000 #elif defined (__MSP430FG477__)
514 000000 #include "msp430fg477.h"
516 000000 #elif defined (__MSP430FG478__)
517 000000 #include "msp430fg478.h"
519 000000 #elif defined (__MSP430FG479__)
520 000000 #include "msp430fg479.h"
522 000000 #elif defined (__MSP430F46161__)
523 000000 #include "msp430f46161.h"
525 000000 #elif defined (__MSP430F46171__)
526 000000 #include "msp430f46171.h"
528 000000 #elif defined (__MSP430F46181__)
529 000000 #include "msp430f46181.h"
531 000000 #elif defined (__MSP430F46191__)
532 000000 #include "msp430f46191.h"
534 000000 #elif defined (__MSP430F4616__)
535 000000 #include "msp430f4616.h"
537 000000 #elif defined (__MSP430F4617__)
538 000000 #include "msp430f4617.h"
540 000000 #elif defined (__MSP430F4618__)
541 000000 #include "msp430f4618.h"
543 000000 #elif defined (__MSP430F4619__)
544 000000 #include "msp430f4619.h"
546 000000 #elif defined (__MSP430FG4616__)
547 000000 #include "msp430fg4616.h"
549 000000 #elif defined (__MSP430FG4617__)
550 000000 #include "msp430fg4617.h"
552 000000 #elif defined (__MSP430FG4618__)
553 000000 #include "msp430fg4618.h"
555 000000 #elif defined (__MSP430FG4619__)
556 000000 #include "msp430fg4619.h"
558 000000 #elif defined (__MSP430F5418__)
559 000000 #include "msp430f5418.h"
561 000000 #elif defined (__MSP430F5419__)
562 000000 #include "msp430f5419.h"
564 000000 #elif defined (__MSP430F5435__)
565 000000 #include "msp430f5435.h"
567 000000 #elif defined (__MSP430F5436__)
568 000000 #include "msp430f5436.h"
570 000000 #elif defined (__MSP430F5437__)
571 000000 #include "msp430f5437.h"
573 000000 #elif defined (__MSP430F5438__)
574 000000 #include "msp430f5438.h"
576 000000 #elif defined (__XMS430F5438__)
577 000000 #include "xms430f5438.h"
579 000000 #elif defined (__MSP430F5418A__)
580 000000 #include "msp430f5418a.h"
582 000000 #elif defined (__MSP430F5419A__)
583 000000 #include "msp430f5419a.h"
585 000000 #elif defined (__MSP430F5435A__)
586 000000 #include "msp430f5435a.h"
588 000000 #elif defined (__MSP430F5436A__)
589 000000 #include "msp430f5436a.h"
591 000000 #elif defined (__MSP430F5437A__)
592 000000 #include "msp430f5437a.h"
594 000000 #elif defined (__MSP430F5438A__)
595 000000 #include "msp430f5438a.h"
597 000000 #elif defined (__MSP430F5304__)
598 000000 #include "msp430f5304.h"
600 000000 #elif defined (__MSP430F5308__)
601 000000 #include "msp430f5308.h"
603 000000 #elif defined (__MSP430F5309__)
604 000000 #include "msp430f5309.h"
606 000000 #elif defined (__MSP430F5310__)
607 000000 #include "msp430f5310.h"
609 000000 #elif defined (__MSP430F5340__)
610 000000 #include "msp430f5340.h"
612 000000 #elif defined (__MSP430F5341__)
613 000000 #include "msp430f5341.h"
615 000000 #elif defined (__MSP430F5342__)
616 000000 #include "msp430f5342.h"
618 000000 #elif defined (__MSP430F5324__)
619 000000 #include "msp430f5324.h"
621 000000 #elif defined (__MSP430F5325__)
622 000000 #include "msp430f5325.h"
624 000000 #elif defined (__MSP430F5326__)
625 000000 #include "msp430f5326.h"
627 000000 #elif defined (__MSP430F5327__)
628 000000 #include "msp430f5327.h"
630 000000 #elif defined (__MSP430F5328__)
631 000000 #include "msp430f5328.h"
633 000000 #elif defined (__MSP430F5329__)
634 000000 #include "msp430f5329.h"
636 000000 #elif defined (__MSP430F5500__)
637 000000 #include "msp430f5500.h"
639 000000 #elif defined (__MSP430F5501__)
640 000000 #include "msp430f5501.h"
642 000000 #elif defined (__MSP430F5502__)
643 000000 #include "msp430f5502.h"
645 000000 #elif defined (__MSP430F5503__)
646 000000 #include "msp430f5503.h"
648 000000 #elif defined (__MSP430F5504__)
649 000000 #include "msp430f5504.h"
651 000000 #elif defined (__MSP430F5505__)
652 000000 #include "msp430f5505.h"
654 000000 #elif defined (__MSP430F5506__)
655 000000 #include "msp430f5506.h"
657 000000 #elif defined (__MSP430F5507__)
658 000000 #include "msp430f5507.h"
660 000000 #elif defined (__MSP430F5508__)
661 000000 #include "msp430f5508.h"
663 000000 #elif defined (__MSP430F5509__)
664 000000 #include "msp430f5509.h"
666 000000 #elif defined (__MSP430F5510__)
667 000000 #include "msp430f5510.h"
669 000000 #elif defined (__MSP430F5513__)
670 000000 #include "msp430f5513.h"
672 000000 #elif defined (__MSP430F5514__)
673 000000 #include "msp430f5514.h"
675 000000 #elif defined (__MSP430F5515__)
676 000000 #include "msp430f5515.h"
678 000000 #elif defined (__MSP430F5517__)
679 000000 #include "msp430f5517.h"
681 000000 #elif defined (__MSP430F5519__)
682 000000 #include "msp430f5519.h"
684 000000 #elif defined (__MSP430F5521__)
685 000000 #include "msp430f5521.h"
687 000000 #elif defined (__MSP430F5522__)
688 000000 #include "msp430f5522.h"
690 000000 #elif defined (__MSP430F5524__)
691 000000 #include "msp430f5524.h"
693 000000 #elif defined (__MSP430F5525__)
694 000000 #include "msp430f5525.h"
696 000000 #elif defined (__MSP430F5526__)
697 000000 #include "msp430f5526.h"
699 000000 #elif defined (__MSP430F5527__)
700 000000 #include "msp430f5527.h"
702 000000 #elif defined (__MSP430F5528__)
703 000000 #include "msp430f5528.h"
705 000000 #elif defined (__MSP430F5529__)
706 000000 #include "msp430f5529.h"
708 000000 #elif defined (__MSP430P112__)
709 000000 #include "msp430p112.h"
711 000000 #elif defined (__MSP430P313__)
712 000000 #include "msp430p313.h"
714 000000 #elif defined (__MSP430P315__)
715 000000 #include "msp430p315.h"
717 000000 #elif defined (__MSP430P315S__)
718 000000 #include "msp430p315s.h"
720 000000 #elif defined (__MSP430P325__)
721 000000 #include "msp430p325.h"
723 000000 #elif defined (__MSP430P337__)
724 000000 #include "msp430p337.h"
726 000000 #elif defined (__CC430F5133__)
727 000000 #include "cc430f5133.h"
729 000000 #elif defined (__CC430F5135__)
730 000000 #include "cc430f5135.h"
732 000000 #elif defined (__CC430F5137__)
733 000000 #include "cc430f5137.h"
735 000000 #elif defined (__CC430F6125__)
736 000000 #include "cc430f6125.h"
738 000000 #elif defined (__CC430F6126__)
739 000000 #include "cc430f6126.h"
741 000000 #elif defined (__CC430F6127__)
742 000000 #include "cc430f6127.h"
744 000000 #elif defined (__CC430F6135__)
745 000000 #include "cc430f6135.h"
747 000000 #elif defined (__CC430F6137__)
748 000000 #include "cc430f6137.h"
750 000000 #elif defined (__MSP430F5630__)
751 000000 #include "msp430f5630.h"
753 000000 #elif defined (__MSP430F5631__)
754 000000 #include "msp430f5631.h"
756 000000 #elif defined (__MSP430F5632__)
757 000000 #include "msp430f5632.h"
759 000000 #elif defined (__MSP430F5633__)
760 000000 #include "msp430f5633.h"
762 000000 #elif defined (__MSP430F5634__)
763 000000 #include "msp430f5634.h"
765 000000 #elif defined (__MSP430F5635__)
766 000000 #include "msp430f5635.h"
768 000000 #elif defined (__MSP430F5636__)
769 000000 #include "msp430f5636.h"
771 000000 #elif defined (__MSP430F5637__)
772 000000 #include "msp430f5637.h"
774 000000 #elif defined (__MSP430F5638__)
775 000000 #include "msp430f5638.h"
777 000000 #elif defined (__MSP430F6630__)
778 000000 #include "msp430f6630.h"
780 000000 #elif defined (__MSP430F6631__)
781 000000 #include "msp430f6631.h"
783 000000 #elif defined (__MSP430F6632__)
784 000000 #include "msp430f6632.h"
786 000000 #elif defined (__MSP430F6633__)
787 000000 #include "msp430f6633.h"
789 000000 #elif defined (__MSP430F6634__)
790 000000 #include "msp430f6634.h"
792 000000 #elif defined (__MSP430F6635__)
793 000000 #include "msp430f6635.h"
795 000000 #elif defined (__MSP430F6636__)
796 000000 #include "msp430f6636.h"
798 000000 #elif defined (__MSP430F6637__)
799 000000 #include "msp430f6637.h"
801 000000 #elif defined (__MSP430F6638__)
802 000000 #include "msp430f6638.h"
804 000000 #elif defined (__MSP430L092__)
805 000000 #include "msp430l092.h"
807 000000 #elif defined (__MSP430C091__)
808 000000 #include "msp430c091.h"
810 000000 #elif defined (__MSP430C092__)
811 000000 #include "msp430c092.h"
813 000000 #elif defined (__MSP430F5131__)
814 000000 #include "msp430f5131.h"
816 000000 #elif defined (__MSP430F5151__)
817 000000 #include "msp430f5151.h"
819 000000 #elif defined (__MSP430F5171__)
820 000000 #include "msp430f5171.h"
822 000000 #elif defined (__MSP430F5132__)
823 000000 #include "msp430f5132.h"
825 000000 #elif defined (__MSP430F5152__)
826 000000 #include "msp430f5152.h"
828 000000 #elif defined (__MSP430F5172__)
829 000000 #include "msp430f5172.h"
831 000000 #elif defined (__MSP430FR5720__)
832 000000 #include "msp430fr5720.h"
834 000000 #elif defined (__MSP430FR5725__)
835 000000 #include "msp430fr5725.h"
837 000000 #elif defined (__MSP430FR5728__)
838 000000 #include "msp430fr5728.h"
840 000000 #elif defined (__MSP430FR5729__)
841 000000 #include "msp430fr5729.h"
843 000000 #elif defined (__MSP430FR5730__)
844 000000 #include "msp430fr5730.h"
846 000000 #elif defined (__MSP430FR5735__)
847 000000 #include "msp430fr5735.h"
849 000000 #elif defined (__MSP430FR5738__)
850 000000 #include "msp430fr5738.h"
852 000000 #elif defined (__MSP430FR5739__)
853 000000 #include "msp430fr5739.h"
855 000000 #elif defined (__MSP430G2211__)
856 000000 #include "msp430g2211.h"
858 000000 #elif defined (__MSP430G2201__)
859 000000 #include "msp430g2201.h"
861 000000 #elif defined (__MSP430G2111__)
862 000000 #include "msp430g2111.h"
864 000000 #elif defined (__MSP430G2101__)
865 000000 #include "msp430g2101.h"
867 000000 #elif defined (__MSP430G2001__)
868 000000 #include "msp430g2001.h"
870 000000 #elif defined (__MSP430G2231__)
871 000000 #include "msp430g2231.h"
873 000000 #elif defined (__MSP430G2221__)
874 000000 #include "msp430g2221.h"
876 000000 #elif defined (__MSP430G2131__)
877 000000 #include "msp430g2131.h"
879 000000 #elif defined (__MSP430G2121__)
880 000000 #include "msp430g2121.h"
882 000000 #elif defined (__MSP430AFE221__)
883 000000 #include "msp430afe221.h"
885 000000 #elif defined (__MSP430AFE231__)
886 000000 #include "msp430afe231.h"
888 000000 #elif defined (__MSP430AFE251__)
889 000000 #include "msp430afe251.h"
891 000000 #elif defined (__MSP430AFE222__)
892 000000 #include "msp430afe222.h"
894 000000 #elif defined (__MSP430AFE232__)
895 000000 #include "msp430afe232.h"
897 000000 #elif defined (__MSP430AFE252__)
898 000000 #include "msp430afe252.h"
900 000000 #elif defined (__MSP430AFE223__)
901 000000 #include "msp430afe223.h"
903 000000 #elif defined (__MSP430AFE233__)
904 000000 #include "msp430afe233.h"
906 000000 #elif defined (__MSP430AFE253__)
907 000000 #include "msp430afe253.h"
909 000000 #elif defined (__MSP430G2102__)
910 000000 #include "msp430g2102.h"
912 000000 #elif defined (__MSP430G2202__)
913 000000 #include "msp430g2202.h"
915 000000 #elif defined (__MSP430G2302__)
916 000000 #include "msp430g2302.h"
918 000000 #elif defined (__MSP430G2402__)
919 000000 #include "msp430g2402.h"
921 000000 #elif defined (__MSP430G2132__)
922 000000 #include "msp430g2132.h"
924 000000 #elif defined (__MSP430G2232__)
925 000000 #include "msp430g2232.h"
927 000000 #elif defined (__MSP430G2332__)
928 000000 #include "msp430g2332.h"
930 000000 #elif defined (__MSP430G2432__)
931 000000 #include "msp430g2432.h"
933 000000 #elif defined (__MSP430G2112__)
934 000000 #include "msp430g2112.h"
936 000000 #elif defined (__MSP430G2212__)
937 000000 #include "msp430g2212.h"
939 000000 #elif defined (__MSP430G2312__)
940 000000 #include "msp430g2312.h"
942 000000 #elif defined (__MSP430G2412__)
943 000000 #include "msp430g2412.h"
945 000000 #elif defined (__MSP430G2152__)
946 000000 #include "msp430g2152.h"
948 000000 #elif defined (__MSP430G2252__)
949 000000 #include "msp430g2252.h"
951 000000 #elif defined (__MSP430G2352__)
952 000000 #include "msp430g2352.h"
954 000000 #elif defined (__MSP430G2452__)
955 000000 #include "msp430g2452.h"
957 000000 #elif defined (__MSP430G2113__)
958 000000 #include "msp430g2113.h"
960 000000 #elif defined (__MSP430G2213__)
961 000000 #include "msp430g2213.h"
963 000000 #elif defined (__MSP430G2313__)
964 000000 #include "msp430g2313.h"
966 000000 #elif defined (__MSP430G2413__)
967 000000 #include "msp430g2413.h"
969 000000 #elif defined (__MSP430G2513__)
970 000000 #include "msp430g2513.h"
972 000000 #elif defined (__MSP430G2153__)
973 000000 #include "msp430g2153.h"
975 000000 #elif defined (__MSP430G2253__)
976 000000 #include "msp430g2253.h"
978 000000 #elif defined (__MSP430G2353__)
979 000000 #include "msp430g2353.h"
981 000000 #elif defined (__MSP430G2453__)
982 000000 #include "msp430g2453.h"
984 000000 #elif defined (__MSP430G2553__)
985 000000 #include "msp430g2553.h"
1 000000 /***********************************************
*********************
2 000000 *
3 000000 * Standard register and bit definitions for the
Texas Instruments
4 000000 * MSP430 microcontroller.
5 000000 *
6 000000 * This file supports assembler and C development
for
7 000000 * MSP430G2553 devices.
8 000000 *
9 000000 * Texas Instruments, Version 1.0
10 000000 *
11 000000 * Rev. 1.0, Setup
12 000000 *
13 000000 ************************************************
********************/
14 000000
15 000000 #ifndef __MSP430G2553
16 000000 #define __MSP430G2553
17 000000
18 000000 #ifdef __IAR_SYSTEMS_ICC__
19 000000 #ifndef _SYSTEM_BUILD
20 000000 #pragma system_include
21 000000 #endif
22 000000 #endif
23 000000
24 000000 #if (((__TID__ >> 8) & 0x7F) != 0x2b) /*
0x2b = 43 dec */
25 000000 #error msp430g2553.h file for use with
ICC430/A430 only
26 000000 #endif
27 000000
28 000000
29 000000 #ifdef __IAR_SYSTEMS_ICC__
30 000000 #include "in430.h"
31 000000 #pragma language=extended
33 000000 #define DEFC(name, address) __no_init volatile
unsigned char name @ address;
34 000000 #define DEFW(name, address) __no_init volatile
unsigned short name @ address;
35 000000 #define DEFXC volatile unsigned char
36 000000 #define DEFXW volatile unsigned short
38 000000 #endif /* __IAR_SYSTEMS_ICC__ */
39 000000
40 000000
41 000000 #ifdef __IAR_SYSTEMS_ASM__
42 000000 #define DEFC(name, address) sfrb name =
address;
43 000000 #define DEFW(name, address) sfrw name =
address;
44 000000
45 000000 #endif /* __IAR_SYSTEMS_ASM__*/
46 000000
47 000000 #ifdef __cplusplus
48 000000 #define READ_ONLY
49 000000 #else
50 000000 #define READ_ONLY const
51 000000 #endif
52 000000
53 000000 /***********************************************
*************
54 000000 * STANDARD BITS
55 000000 ************************************************
************/
56 000000
57 000000 #define BIT0 (0x0001u)
58 000000 #define BIT1 (0x0002u)
59 000000 #define BIT2 (0x0004u)
60 000000 #define BIT3 (0x0008u)
61 000000 #define BIT4 (0x0010u)
62 000000 #define BIT5 (0x0020u)
63 000000 #define BIT6 (0x0040u)
64 000000 #define BIT7 (0x0080u)
65 000000 #define BIT8 (0x0100u)
66 000000 #define BIT9 (0x0200u)
67 000000 #define BITA (0x0400u)
68 000000 #define BITB (0x0800u)
69 000000 #define BITC (0x1000u)
70 000000 #define BITD (0x2000u)
71 000000 #define BITE (0x4000u)
72 000000 #define BITF (0x8000u)
73 000000
74 000000 /***********************************************
*************
75 000000 * STATUS REGISTER BITS
76 000000 ************************************************
************/
77 000000
78 000000 #define C (0x0001u)
79 000000 #define Z (0x0002u)
80 000000 #define N (0x0004u)
81 000000 #define V (0x0100u)
82 000000 #define GIE (0x0008u)
83 000000 #define CPUOFF (0x0010u)
84 000000 #define OSCOFF (0x0020u)
85 000000 #define SCG0 (0x0040u)
86 000000 #define SCG1 (0x0080u)
87 000000
88 000000 /* Low Power Modes coded with Bits 4-7 in SR
*/
89 000000
90 000000 #ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines
for assembler */
91 000000 #define LPM0 (CPUOFF)
92 000000 #define LPM1 (SCG0+CPUOFF)
93 000000 #define LPM2 (SCG1+CPUOFF)
94 000000 #define LPM3 (SCG1+SCG0+CPUOFF)
95 000000 #define LPM4 (SCG1+SCG0+OSCOFF+CP
UOFF)
96 000000 /* End #defines for assembler */
97 000000
98 000000 #else /* Begin #defines for C */
99 000000 #define LPM0_bits (CPUOFF)
100 000000 #define LPM1_bits (SCG0+CPUOFF)
101 000000 #define LPM2_bits (SCG1+CPUOFF)
102 000000 #define LPM3_bits (SCG1+SCG0+CPUOFF)
103 000000 #define LPM4_bits (SCG1+SCG0+OSCOFF+CP
UOFF)
105 000000 #include "in430.h"
107 000000 #define LPM0 _BIS_SR(LPM0_bits) /*
Enter Low Power Mode 0 */
108 000000 #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit
Low Power Mode 0 */
109 000000 #define LPM1 _BIS_SR(LPM1_bits) /*
Enter Low Power Mode 1 */
110 000000 #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit
Low Power Mode 1 */
111 000000 #define LPM2 _BIS_SR(LPM2_bits) /*
Enter Low Power Mode 2 */
112 000000 #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit
Low Power Mode 2 */
113 000000 #define LPM3 _BIS_SR(LPM3_bits) /*
Enter Low Power Mode 3 */
114 000000 #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit
Low Power Mode 3 */
115 000000 #define LPM4 _BIS_SR(LPM4_bits) /*
Enter Low Power Mode 4 */
116 000000 #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit
Low Power Mode 4 */
117 000000 #endif /* End #defines for C */
118 000000
119 000000 /***********************************************
*************
120 000000 * PERIPHERAL FILE MAP
121 000000 ************************************************
************/
122 000000
123 000000 /***********************************************
*************
124 000000 * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL
BITS
125 000000 ************************************************
************/
126 000000
127 000000 #define IE1_ (0x0000u) /*
Interrupt Enable 1 */
128 000000 DEFC( IE1 , IE1_)
129 000000 #define WDTIE (0x01) /*
Watchdog Interrupt Enable */
130 000000 #define OFIE (0x02) /* Osc.
Fault Interrupt Enable */
131 000000 #define NMIIE (0x10) /* NMI
Interrupt Enable */
132 000000 #define ACCVIE (0x20) /* Flash
Access Violation Interrupt Enable */
133 000000
134 000000 #define IFG1_ (0x0002u) /*
Interrupt Flag 1 */
135 000000 DEFC( IFG1 , IFG1_)
136 000000 #define WDTIFG (0x01) /*
Watchdog Interrupt Flag */
137 000000 #define OFIFG (0x02) /* Osc.
Fault Interrupt Flag */
138 000000 #define PORIFG (0x04) /* Power
On Interrupt Flag */
139 000000 #define RSTIFG (0x08) /* Reset
Interrupt Flag */
140 000000 #define NMIIFG (0x10) /* NMI
Interrupt Flag */
141 000000
142 000000 #define IE2_ (0x0001u) /*
Interrupt Enable 2 */
143 000000 DEFC( IE2 , IE2_)
144 000000 #define UC0IE IE2
145 000000 #define UCA0RXIE (0x01)
146 000000 #define UCA0TXIE (0x02)
147 000000 #define UCB0RXIE (0x04)
148 000000 #define UCB0TXIE (0x08)
149 000000
150 000000 #define IFG2_ (0x0003u) /*
Interrupt Flag 2 */
151 000000 DEFC( IFG2 , IFG2_)
152 000000 #define UC0IFG IFG2
153 000000 #define UCA0RXIFG (0x01)
154 000000 #define UCA0TXIFG (0x02)
155 000000 #define UCB0RXIFG (0x04)
156 000000 #define UCB0TXIFG (0x08)
157 000000
158 000000 /***********************************************
*************
159 000000 * ADC10
160 000000 ************************************************
************/
161 000000 #define __MSP430_HAS_ADC10__ /*
Definition to show that Module is available
*/
162 000000
163 000000 #define ADC10DTC0_ (0x0048u) /*
ADC10 Data Transfer Control 0 */
164 000000 DEFC( ADC10DTC0 , ADC10DTC0_)
165 000000 #define ADC10DTC1_ (0x0049u) /*
ADC10 Data Transfer Control 1 */
166 000000 DEFC( ADC10DTC1 , ADC10DTC1_)
167 000000 #define ADC10AE0_ (0x004Au) /*
ADC10 Analog Enable 0 */
168 000000 DEFC( ADC10AE0 , ADC10AE0_)
169 000000
170 000000 #define ADC10CTL0_ (0x01B0u) /*
ADC10 Control 0 */
171 000000 DEFW( ADC10CTL0 , ADC10CTL0_)
172 000000 #define ADC10CTL1_ (0x01B2u) /*
ADC10 Control 1 */
173 000000 DEFW( ADC10CTL1 , ADC10CTL1_)
174 000000 #define ADC10MEM_ (0x01B4u) /*
ADC10 Memory */
175 000000 DEFW( ADC10MEM , ADC10MEM_)
176 000000 #define ADC10SA_ (0x01BCu) /*
ADC10 Data Transfer Start Address */
177 000000 DEFW( ADC10SA , ADC10SA_)
178 000000
179 000000 /* ADC10CTL0 */
180 000000 #define ADC10SC (0x001) /* ADC10
Start Conversion */
181 000000 #define ENC (0x002) /* ADC10
Enable Conversion */
182 000000 #define ADC10IFG (0x004) /* ADC10
Interrupt Flag */
183 000000 #define ADC10IE (0x008) /* ADC10
Interrupt Enalbe */
184 000000 #define ADC10ON (0x010) /* ADC10
On/Enable */
185 000000 #define REFON (0x020) /* ADC10
Reference on */
186 000000 #define REF2_5V (0x040) /* ADC10
Ref 0:1.5V / 1:2.5V */
187 000000 #define MSC (0x080) /* ADC10
Multiple SampleConversion */
188 000000 #define REFBURST (0x100) /* ADC10
Reference Burst Mode */
189 000000 #define REFOUT (0x200) /* ADC10
Enalbe output of Ref. */
190 000000 #define ADC10SR (0x400) /* ADC10
Sampling Rate 0:200ksps / 1:50ksps */
191 000000 #define ADC10SHT0 (0x800) /* ADC10
Sample Hold Select Bit: 0 */
192 000000 #define ADC10SHT1 (0x1000u) /*
ADC10 Sample Hold Select Bit: 1 */
193 000000 #define SREF0 (0x2000u) /*
ADC10 Reference Select Bit: 0 */
194 000000 #define SREF1 (0x4000u) /*
ADC10 Reference Select Bit: 1 */
195 000000 #define SREF2 (0x8000u) /*
ADC10 Reference Select Bit: 2 */
196 000000 #define ADC10SHT_0 (0*0x800u) /* 4 x
ADC10CLKs */
197 000000 #define ADC10SHT_1 (1*0x800u) /* 8 x
ADC10CLKs */
198 000000 #define ADC10SHT_2 (2*0x800u) /* 16 x
ADC10CLKs */
199 000000 #define ADC10SHT_3 (3*0x800u) /* 64 x
ADC10CLKs */
200 000000
201 000000 #define SREF_0 (0*0x2000u) /* VR+
= AVCC and VR- = AVSS */
202 000000 #define SREF_1 (1*0x2000u) /* VR+
= VREF+ and VR- = AVSS */
203 000000 #define SREF_2 (2*0x2000u) /* VR+
= VEREF+ and VR- = AVSS */
204 000000 #define SREF_3 (3*0x2000u) /* VR+
= VEREF+ and VR- = AVSS */
205 000000 #define SREF_4 (4*0x2000u) /* VR+
= AVCC and VR- = VREF-/VEREF- */
206 000000 #define SREF_5 (5*0x2000u) /* VR+
= VREF+ and VR- = VREF-/VEREF- */
207 000000 #define SREF_6 (6*0x2000u) /* VR+
= VEREF+ and VR- = VREF-/VEREF- */
208 000000 #define SREF_7 (7*0x2000u) /* VR+
= VEREF+ and VR- = VREF-/VEREF- */
209 000000
210 000000 /* ADC10CTL1 */
211 000000 #define ADC10BUSY (0x0001u) /*
ADC10 BUSY */
212 000000 #define CONSEQ0 (0x0002u) /*
ADC10 Conversion Sequence Select 0 */
213 000000 #define CONSEQ1 (0x0004u) /*
ADC10 Conversion Sequence Select 1 */
214 000000 #define ADC10SSEL0 (0x0008u) /*
ADC10 Clock Source Select Bit: 0 */
215 000000 #define ADC10SSEL1 (0x0010u) /*
ADC10 Clock Source Select Bit: 1 */
216 000000 #define ADC10DIV0 (0x0020u) /*
ADC10 Clock Divider Select Bit: 0 */
217 000000 #define ADC10DIV1 (0x0040u) /*
ADC10 Clock Divider Select Bit: 1 */
218 000000 #define ADC10DIV2 (0x0080u) /*
ADC10 Clock Divider Select Bit: 2 */
219 000000 #define ISSH (0x0100u) /*
ADC10 Invert Sample Hold Signal */
220 000000 #define ADC10DF (0x0200u) /*
ADC10 Data Format 0:binary 1:2's complement
*/
221 000000 #define SHS0 (0x0400u) /*
ADC10 Sample/Hold Source Bit: 0 */
222 000000 #define SHS1 (0x0800u) /*
ADC10 Sample/Hold Source Bit: 1 */
223 000000 #define INCH0 (0x1000u) /*
ADC10 Input Channel Select Bit: 0 */
224 000000 #define INCH1 (0x2000u) /*
ADC10 Input Channel Select Bit: 1 */
225 000000 #define INCH2 (0x4000u) /*
ADC10 Input Channel Select Bit: 2 */
226 000000 #define INCH3 (0x8000u) /*
ADC10 Input Channel Select Bit: 3 */
227 000000
228 000000 #define CONSEQ_0 (0*2u) /*
Single channel single conversion */
229 000000 #define CONSEQ_1 (1*2u) /*
Sequence of channels */
230 000000 #define CONSEQ_2 (2*2u) /*
Repeat single channel */
231 000000 #define CONSEQ_3 (3*2u) /*
Repeat sequence of channels */
232 000000
233 000000 #define ADC10SSEL_0 (0*8u) /*
ADC10OSC */
234 000000 #define ADC10SSEL_1 (1*8u) /* ACLK
*/
235 000000 #define ADC10SSEL_2 (2*8u) /* MCLK
*/
236 000000 #define ADC10SSEL_3 (3*8u) /*
SMCLK */
237 000000
238 000000 #define ADC10DIV_0 (0*0x20u) /*
ADC10 Clock Divider Select 0 */
239 000000 #define ADC10DIV_1 (1*0x20u) /*
ADC10 Clock Divider Select 1 */
240 000000 #define ADC10DIV_2 (2*0x20u) /*
ADC10 Clock Divider Select 2 */
241 000000 #define ADC10DIV_3 (3*0x20u) /*
ADC10 Clock Divider Select 3 */
242 000000 #define ADC10DIV_4 (4*0x20u) /*
ADC10 Clock Divider Select 4 */
243 000000 #define ADC10DIV_5 (5*0x20u) /*
ADC10 Clock Divider Select 5 */
244 000000 #define ADC10DIV_6 (6*0x20u) /*
ADC10 Clock Divider Select 6 */
245 000000 #define ADC10DIV_7 (7*0x20u) /*
ADC10 Clock Divider Select 7 */
246 000000
247 000000 #define SHS_0 (0*0x400u) /*
ADC10SC */
248 000000 #define SHS_1 (1*0x400u) /* TA3
OUT1 */
249 000000 #define SHS_2 (2*0x400u) /* TA3
OUT0 */
250 000000 #define SHS_3 (3*0x400u) /* TA3
OUT2 */
251 000000
252 000000 #define INCH_0 (0*0x1000u) /*
Selects Channel 0 */
253 000000 #define INCH_1 (1*0x1000u) /*
Selects Channel 1 */
254 000000 #define INCH_2 (2*0x1000u) /*
Selects Channel 2 */
255 000000 #define INCH_3 (3*0x1000u) /*
Selects Channel 3 */
256 000000 #define INCH_4 (4*0x1000u) /*
Selects Channel 4 */
257 000000 #define INCH_5 (5*0x1000u) /*
Selects Channel 5 */
258 000000 #define INCH_6 (6*0x1000u) /*
Selects Channel 6 */
259 000000 #define INCH_7 (7*0x1000u) /*
Selects Channel 7 */
260 000000 #define INCH_8 (8*0x1000u) /*
Selects Channel 8 */
261 000000 #define INCH_9 (9*0x1000u) /*
Selects Channel 9 */
262 000000 #define INCH_10 (10*0x1000u) /*
Selects Channel 10 */
263 000000 #define INCH_11 (11*0x1000u) /*
Selects Channel 11 */
264 000000 #define INCH_12 (12*0x1000u) /*
Selects Channel 12 */
265 000000 #define INCH_13 (13*0x1000u) /*
Selects Channel 13 */
266 000000 #define INCH_14 (14*0x1000u) /*
Selects Channel 14 */
267 000000 #define INCH_15 (15*0x1000u) /*
Selects Channel 15 */
268 000000
269 000000 /* ADC10DTC0 */
270 000000 #define ADC10FETCH (0x001) /* This
bit should normally be reset */
271 000000 #define ADC10B1 (0x002) /* ADC10
block one */
272 000000 #define ADC10CT (0x004) /* ADC10
continuous transfer */
273 000000 #define ADC10TB (0x008) /* ADC10
two-block mode */
274 000000 #define ADC10DISABLE (0x000) /*
ADC10DTC1 */
275 000000
276 000000 /***********************************************
*************
277 000000 * Basic Clock Module
278 000000 ************************************************
************/
279 000000 #define __MSP430_HAS_BC2__ /*
Definition to show that Module is available
*/
280 000000
281 000000 #define DCOCTL_ (0x0056u) /* DCO
Clock Frequency Control */
282 000000 DEFC( DCOCTL , DCOCTL_)
283 000000 #define BCSCTL1_ (0x0057u) /* Basic
Clock System Control 1 */
284 000000 DEFC( BCSCTL1 , BCSCTL1_)
285 000000 #define BCSCTL2_ (0x0058u) /* Basic
Clock System Control 2 */
286 000000 DEFC( BCSCTL2 , BCSCTL2_)
287 000000 #define BCSCTL3_ (0x0053u) /* Basic
Clock System Control 3 */
288 000000 DEFC( BCSCTL3 , BCSCTL3_)
289 000000
290 000000 #define MOD0 (0x01) /*
Modulation Bit 0 */
291 000000 #define MOD1 (0x02) /*
Modulation Bit 1 */
292 000000 #define MOD2 (0x04) /*
Modulation Bit 2 */
293 000000 #define MOD3 (0x08) /*
Modulation Bit 3 */
294 000000 #define MOD4 (0x10) /*
Modulation Bit 4 */
295 000000 #define DCO0 (0x20) /* DCO
Select Bit 0 */
296 000000 #define DCO1 (0x40) /* DCO
Select Bit 1 */
297 000000 #define DCO2 (0x80) /* DCO
Select Bit 2 */
298 000000
299 000000 #define RSEL0 (0x01) /* Range
Select Bit 0 */
300 000000 #define RSEL1 (0x02) /* Range
Select Bit 1 */
301 000000 #define RSEL2 (0x04) /* Range
Select Bit 2 */
302 000000 #define RSEL3 (0x08) /* Range
Select Bit 3 */
303 000000 #define DIVA0 (0x10) /* ACLK
Divider 0 */
304 000000 #define DIVA1 (0x20) /* ACLK
Divider 1 */
305 000000 #define XTS (0x40) /* LFXTCLK
0:Low Freq. / 1: High Freq. */
306 000000 #define XT2OFF (0x80) /* Enable
XT2CLK */
307 000000
308 000000 #define DIVA_0 (0x00) /* ACLK
Divider 0: /1 */
309 000000 #define DIVA_1 (0x10) /* ACLK
Divider 1: /2 */
310 000000 #define DIVA_2 (0x20) /* ACLK
Divider 2: /4 */
311 000000 #define DIVA_3 (0x30) /* ACLK
Divider 3: /8 */
312 000000
313 000000 #define DIVS0 (0x02) /* SMCLK
Divider 0 */
314 000000 #define DIVS1 (0x04) /* SMCLK
Divider 1 */
315 000000 #define SELS (0x08) /* SMCLK
Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK
*/
316 000000 #define DIVM0 (0x10) /* MCLK
Divider 0 */
317 000000 #define DIVM1 (0x20) /* MCLK
Divider 1 */
318 000000 #define SELM0 (0x40) /* MCLK
Source Select 0 */
319 000000 #define SELM1 (0x80) /* MCLK
Source Select 1 */
320 000000
321 000000 #define DIVS_0 (0x00) /* SMCLK
Divider 0: /1 */
322 000000 #define DIVS_1 (0x02) /* SMCLK
Divider 1: /2 */
323 000000 #define DIVS_2 (0x04) /* SMCLK
Divider 2: /4 */
324 000000 #define DIVS_3 (0x06) /* SMCLK
Divider 3: /8 */
325 000000
326 000000 #define DIVM_0 (0x00) /* MCLK
Divider 0: /1 */
327 000000 #define DIVM_1 (0x10) /* MCLK
Divider 1: /2 */
328 000000 #define DIVM_2 (0x20) /* MCLK
Divider 2: /4 */
329 000000 #define DIVM_3 (0x30) /* MCLK
Divider 3: /8 */
330 000000
331 000000 #define SELM_0 (0x00) /* MCLK
Source Select 0: DCOCLK */
332 000000 #define SELM_1 (0x40) /* MCLK
Source Select 1: DCOCLK */
333 000000 #define SELM_2 (0x80) /* MCLK
Source Select 2: XT2CLK/LFXTCLK */
334 000000 #define SELM_3 (0xC0) /* MCLK
Source Select 3: LFXTCLK */
335 000000
336 000000 #define LFXT1OF (0x01) /* Low/high
Frequency Oscillator Fault Flag */
337 000000 #define XT2OF (0x02) /* High
frequency oscillator 2 fault flag */
338 000000 #define XCAP0 (0x04) /* XIN/XOUT
Cap 0 */
339 000000 #define XCAP1 (0x08) /* XIN/XOUT
Cap 1 */
340 000000 #define LFXT1S0 (0x10) /* Mode 0
for LFXT1 (XTS = 0) */
341 000000 #define LFXT1S1 (0x20) /* Mode 1
for LFXT1 (XTS = 0) */
342 000000 #define XT2S0 (0x40) /* Mode 0
for XT2 */
343 000000 #define XT2S1 (0x80) /* Mode 1
for XT2 */
344 000000
345 000000 #define XCAP_0 (0x00) /* XIN/XOUT
Cap : 0 pF */
346 000000 #define XCAP_1 (0x04) /* XIN/XOUT
Cap : 6 pF */
347 000000 #define XCAP_2 (0x08) /* XIN/XOUT
Cap : 10 pF */
348 000000 #define XCAP_3 (0x0C) /* XIN/XOUT
Cap : 12.5 pF */
349 000000
350 000000 #define LFXT1S_0 (0x00) /* Mode 0
for LFXT1 : Normal operation */
351 000000 #define LFXT1S_1 (0x10) /* Mode 1
for LFXT1 : Reserved */
352 000000 #define LFXT1S_2 (0x20) /* Mode 2
for LFXT1 : VLO */
353 000000 #define LFXT1S_3 (0x30) /* Mode 3
for LFXT1 : Digital input signal */
354 000000
355 000000 #define XT2S_0 (0x00) /* Mode 0
for XT2 : 0.4 - 1 MHz */
356 000000 #define XT2S_1 (0x40) /* Mode 1
for XT2 : 1 - 4 MHz */
357 000000 #define XT2S_2 (0x80) /* Mode 2
for XT2 : 2 - 16 MHz */
358 000000 #define XT2S_3 (0xC0) /* Mode 3
for XT2 : Digital input signal */
359 000000
360 000000 /***********************************************
*************
361 000000 * Comparator A
362 000000 ************************************************
************/
363 000000 #define __MSP430_HAS_CAPLUS__ /*
Definition to show that Module is available
*/
364 000000
365 000000 #define CACTL1_ (0x0059u) /*
Comparator A Control 1 */
366 000000 DEFC( CACTL1 , CACTL1_)
367 000000 #define CACTL2_ (0x005Au) /*
Comparator A Control 2 */
368 000000 DEFC( CACTL2 , CACTL2_)
369 000000 #define CAPD_ (0x005Bu) /*
Comparator A Port Disable */
370 000000 DEFC( CAPD , CAPD_)
371 000000
372 000000 #define CAIFG (0x01) /* Comp. A
Interrupt Flag */
373 000000 #define CAIE (0x02) /* Comp. A
Interrupt Enable */
374 000000 #define CAIES (0x04) /* Comp. A
Int. Edge Select: 0:rising / 1:falling
*/
375 000000 #define CAON (0x08) /* Comp. A
enable */
376 000000 #define CAREF0 (0x10) /* Comp. A
Internal Reference Select 0 */
377 000000 #define CAREF1 (0x20) /* Comp. A
Internal Reference Select 1 */
378 000000 #define CARSEL (0x40) /* Comp. A
Internal Reference Enable */
379 000000 #define CAEX (0x80) /* Comp. A
Exchange Inputs */
380 000000
381 000000 #define CAREF_0 (0x00) /* Comp. A
Int. Ref. Select 0 : Off */
382 000000 #define CAREF_1 (0x10) /* Comp. A
Int. Ref. Select 1 : 0.25*Vcc */
383 000000 #define CAREF_2 (0x20) /* Comp. A
Int. Ref. Select 2 : 0.5*Vcc */
384 000000 #define CAREF_3 (0x30) /* Comp. A
Int. Ref. Select 3 : Vt*/
385 000000
386 000000 #define CAOUT (0x01) /* Comp. A
Output */
387 000000 #define CAF (0x02) /* Comp. A
Enable Output Filter */
388 000000 #define P2CA0 (0x04) /* Comp. A
+Terminal Multiplexer */
389 000000 #define P2CA1 (0x08) /* Comp. A
-Terminal Multiplexer */
390 000000 #define P2CA2 (0x10) /* Comp. A
-Terminal Multiplexer */
391 000000 #define P2CA3 (0x20) /* Comp. A
-Terminal Multiplexer */
392 000000 #define P2CA4 (0x40) /* Comp. A
+Terminal Multiplexer */
393 000000 #define CASHORT (0x80) /* Comp. A
Short + and - Terminals */
394 000000
395 000000 #define CAPD0 (0x01) /* Comp. A
Disable Input Buffer of Port Register .0
*/
396 000000 #define CAPD1 (0x02) /* Comp. A
Disable Input Buffer of Port Register .1
*/
397 000000 #define CAPD2 (0x04) /* Comp. A
Disable Input Buffer of Port Register .2
*/
398 000000 #define CAPD3 (0x08) /* Comp. A
Disable Input Buffer of Port Register .3
*/
399 000000 #define CAPD4 (0x10) /* Comp. A
Disable Input Buffer of Port Register .4
*/
400 000000 #define CAPD5 (0x20) /* Comp. A
Disable Input Buffer of Port Register .5
*/
401 000000 #define CAPD6 (0x40) /* Comp. A
Disable Input Buffer of Port Register .6
*/
402 000000 #define CAPD7 (0x80) /* Comp. A
Disable Input Buffer of Port Register .7
*/
403 000000
404 000000 /***********************************************
**************
405 000000 * Flash Memory
406 000000 ************************************************
*************/
407 000000 #define __MSP430_HAS_FLASH2__ /*
Definition to show that Module is available
*/
408 000000
409 000000 #define FCTL1_ (0x0128u) /* FLASH
Control 1 */
410 000000 DEFW( FCTL1 , FCTL1_)
411 000000 #define FCTL2_ (0x012Au) /* FLASH
Control 2 */
412 000000 DEFW( FCTL2 , FCTL2_)
413 000000 #define FCTL3_ (0x012Cu) /* FLASH
Control 3 */
414 000000 DEFW( FCTL3 , FCTL3_)
415 000000
416 000000 #define FRKEY (0x9600u) /* Flash
key returned by read */
417 000000 #define FWKEY (0xA500u) /* Flash
key for write */
418 000000 #define FXKEY (0x3300u) /* for
use with XOR instruction */
419 000000
420 000000 #define ERASE (0x0002u) /* Enable
bit for Flash segment erase */
421 000000 #define MERAS (0x0004u) /* Enable
bit for Flash mass erase */
422 000000 #define WRT (0x0040u) /* Enable
bit for Flash write */
423 000000 #define BLKWRT (0x0080u) /* Enable
bit for Flash segment write */
424 000000 #define SEGWRT (0x0080u) /* old
definition */ /* Enable bit for Flash segment
write */
425 000000
426 000000 #define FN0 (0x0001u) /* Divide
Flash clock by 1 to 64 using FN0 to FN5
according to: */
427 000000 #define FN1 (0x0002u) /*
32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 +
1 */
428 000000 #ifndef FN2
429 000000 #define FN2 (0x0004u)
430 000000 #endif
431 000000 #ifndef FN3
432 000000 #define FN3 (0x0008u)
433 000000 #endif
434 000000 #ifndef FN4
435 000000 #define FN4 (0x0010u)
436 000000 #endif
437 000000 #define FN5 (0x0020u)
438 000000 #define FSSEL0 (0x0040u) /* Flash
clock select 0 */ /* to distinguish from
USART SSELx */
439 000000 #define FSSEL1 (0x0080u) /* Flash
clock select 1 */
440 000000
441 000000 #define FSSEL_0 (0x0000u) /* Flash
clock select: 0 - ACLK */
442 000000 #define FSSEL_1 (0x0040u) /* Flash
clock select: 1 - MCLK */
443 000000 #define FSSEL_2 (0x0080u) /* Flash
clock select: 2 - SMCLK */
444 000000 #define FSSEL_3 (0x00C0u) /* Flash
clock select: 3 - SMCLK */
445 000000
446 000000 #define BUSY (0x0001u) /* Flash
busy: 1 */
447 000000 #define KEYV (0x0002u) /* Flash
Key violation flag */
448 000000 #define ACCVIFG (0x0004u) /* Flash
Access violation flag */
449 000000 #define WAIT (0x0008u) /* Wait
flag for segment write */
450 000000 #define LOCK (0x0010u) /* Lock
bit: 1 - Flash is locked (read only) */
451 000000 #define EMEX (0x0020u) /* Flash
Emergency Exit */
452 000000 #define LOCKA (0x0040u) /*
Segment A Lock bit: read = 1 - Segment is
locked (read only) */
453 000000 #define FAIL (0x0080u) /* Last
Program or Erase failed */
454 000000
455 000000 /***********************************************
*************
456 000000 * DIGITAL I/O Port1/2 Pull up / Pull down
Resistors
457 000000 ************************************************
************/
458 000000 #define __MSP430_HAS_PORT1_R__ /*
Definition to show that Module is available
*/
459 000000 #define __MSP430_HAS_PORT2_R__ /*
Definition to show that Module is available
*/
460 000000
461 000000 #define P1IN_ (0x0020u) /* Port 1
Input */
462 000000 READ_ONLY DEFC( P1IN , P1IN_)
463 000000 #define P1OUT_ (0x0021u) /* Port 1
Output */
464 000000 DEFC( P1OUT , P1OUT_)
465 000000 #define P1DIR_ (0x0022u) /* Port 1
Direction */
466 000000 DEFC( P1DIR , P1DIR_)
467 000000 #define P1IFG_ (0x0023u) /* Port 1
Interrupt Flag */
468 000000 DEFC( P1IFG , P1IFG_)
469 000000 #define P1IES_ (0x0024u) /* Port 1
Interrupt Edge Select */
470 000000 DEFC( P1IES , P1IES_)
471 000000 #define P1IE_ (0x0025u) /* Port 1
Interrupt Enable */
472 000000 DEFC( P1IE , P1IE_)
473 000000 #define P1SEL_ (0x0026u) /* Port 1
Selection */
474 000000 DEFC( P1SEL , P1SEL_)
475 000000 #define P1SEL2_ (0x0041u) /* Port 1
Selection 2 */
476 000000 DEFC( P1SEL2 , P1SEL2_)
477 000000 #define P1REN_ (0x0027u) /* Port 1
Resistor Enable */
478 000000 DEFC( P1REN , P1REN_)
479 000000
480 000000 #define P2IN_ (0x0028u) /* Port 2
Input */
481 000000 READ_ONLY DEFC( P2IN , P2IN_)
482 000000 #define P2OUT_ (0x0029u) /* Port 2
Output */
483 000000 DEFC( P2OUT , P2OUT_)
484 000000 #define P2DIR_ (0x002Au) /* Port 2
Direction */
485 000000 DEFC( P2DIR , P2DIR_)
486 000000 #define P2IFG_ (0x002Bu) /* Port 2
Interrupt Flag */
487 000000 DEFC( P2IFG , P2IFG_)
488 000000 #define P2IES_ (0x002Cu) /* Port 2
Interrupt Edge Select */
489 000000 DEFC( P2IES , P2IES_)
490 000000 #define P2IE_ (0x002Du) /* Port 2
Interrupt Enable */
491 000000 DEFC( P2IE , P2IE_)
492 000000 #define P2SEL_ (0x002Eu) /* Port 2
Selection */
493 000000 DEFC( P2SEL , P2SEL_)
494 000000 #define P2SEL2_ (0x0042u) /* Port 2
Selection 2 */
495 000000 DEFC( P2SEL2 , P2SEL2_)
496 000000 #define P2REN_ (0x002Fu) /* Port 2
Resistor Enable */
497 000000 DEFC( P2REN , P2REN_)
498 000000
499 000000 /***********************************************
*************
500 000000 * DIGITAL I/O Port3 Pull up / Pull down
Resistors
501 000000 ************************************************
************/
502 000000 #define __MSP430_HAS_PORT3_R__ /*
Definition to show that Module is available
*/
503 000000
504 000000 #define P3IN_ (0x0018u) /* Port 3
Input */
505 000000 READ_ONLY DEFC( P3IN , P3IN_)
506 000000 #define P3OUT_ (0x0019u) /* Port 3
Output */
507 000000 DEFC( P3OUT , P3OUT_)
508 000000 #define P3DIR_ (0x001Au) /* Port 3
Direction */
509 000000 DEFC( P3DIR , P3DIR_)
510 000000 #define P3SEL_ (0x001Bu) /* Port 3
Selection */
511 000000 DEFC( P3SEL , P3SEL_)
512 000000 #define P3SEL2_ (0x0043u) /* Port 3
Selection 2 */
513 000000 DEFC( P3SEL2 , P3SEL2_)
514 000000 #define P3REN_ (0x0010u) /* Port 3
Resistor Enable */
515 000000 DEFC( P3REN , P3REN_)
516 000000
517 000000 /***********************************************
*************
518 000000 * Timer0_A3
519 000000 ************************************************
************/
520 000000 #define __MSP430_HAS_TA3__ /*
Definition to show that Module is available
*/
521 000000
522 000000 #define TA0IV_ (0x012Eu) /*
Timer0_A3 Interrupt Vector Word */
523 000000 READ_ONLY DEFW( TA0IV , TA0IV_)
524 000000 #define TA0CTL_ (0x0160u) /*
Timer0_A3 Control */
525 000000 DEFW( TA0CTL , TA0CTL_)
526 000000 #define TA0CCTL0_ (0x0162u) /*
Timer0_A3 Capture/Compare Control 0 */
527 000000 DEFW( TA0CCTL0 , TA0CCTL0_)
528 000000 #define TA0CCTL1_ (0x0164u) /*
Timer0_A3 Capture/Compare Control 1 */
529 000000 DEFW( TA0CCTL1 , TA0CCTL1_)
530 000000 #define TA0CCTL2_ (0x0166u) /*
Timer0_A3 Capture/Compare Control 2 */
531 000000 DEFW( TA0CCTL2 , TA0CCTL2_)
532 000000 #define TA0R_ (0x0170u) /*
Timer0_A3 */
533 000000 DEFW( TA0R , TA0R_)
534 000000 #define TA0CCR0_ (0x0172u) /*
Timer0_A3 Capture/Compare 0 */
535 000000 DEFW( TA0CCR0 , TA0CCR0_)
536 000000 #define TA0CCR1_ (0x0174u) /*
Timer0_A3 Capture/Compare 1 */
537 000000 DEFW( TA0CCR1 , TA0CCR1_)
538 000000 #define TA0CCR2_ (0x0176u) /*
Timer0_A3 Capture/Compare 2 */
539 000000 DEFW( TA0CCR2 , TA0CCR2_)
540 000000
541 000000 /* Alternate register names */
542 000000 #define TAIV TA0IV /* Timer A
Interrupt Vector Word */
543 000000 #define TACTL TA0CTL /* Timer A
Control */
544 000000 #define TACCTL0 TA0CCTL0 /* Timer A
Capture/Compare Control 0 */
545 000000 #define TACCTL1 TA0CCTL1 /* Timer A
Capture/Compare Control 1 */
546 000000 #define TACCTL2 TA0CCTL2 /* Timer A
Capture/Compare Control 2 */
547 000000 #define TAR TA0R /* Timer A
*/
548 000000 #define TACCR0 TA0CCR0 /* Timer A
Capture/Compare 0 */
549 000000 #define TACCR1 TA0CCR1 /* Timer A
Capture/Compare 1 */
550 000000 #define TACCR2 TA0CCR2 /* Timer A
Capture/Compare 2 */
551 000000 #define TAIV_ TA0IV_ /* Timer A
Interrupt Vector Word */
552 000000 #define TACTL_ TA0CTL_ /* Timer A
Control */
553 000000 #define TACCTL0_ TA0CCTL0_ /* Timer A
Capture/Compare Control 0 */
554 000000 #define TACCTL1_ TA0CCTL1_ /* Timer A
Capture/Compare Control 1 */
555 000000 #define TACCTL2_ TA0CCTL2_ /* Timer A
Capture/Compare Control 2 */
556 000000 #define TAR_ TA0R_ /* Timer A
*/
557 000000 #define TACCR0_ TA0CCR0_ /* Timer A
Capture/Compare 0 */
558 000000 #define TACCR1_ TA0CCR1_ /* Timer A
Capture/Compare 1 */
559 000000 #define TACCR2_ TA0CCR2_ /* Timer A
Capture/Compare 2 */
560 000000
561 000000 /* Alternate register names 2 */
562 000000 #define CCTL0 TACCTL0 /* Timer A
Capture/Compare Control 0 */
563 000000 #define CCTL1 TACCTL1 /* Timer A
Capture/Compare Control 1 */
564 000000 #define CCTL2 TACCTL2 /* Timer A
Capture/Compare Control 2 */
565 000000 #define CCR0 TACCR0 /* Timer A
Capture/Compare 0 */
566 000000 #define CCR1 TACCR1 /* Timer A
Capture/Compare 1 */
567 000000 #define CCR2 TACCR2 /* Timer A
Capture/Compare 2 */
568 000000 #define CCTL0_ TACCTL0_ /* Timer A
Capture/Compare Control 0 */
569 000000 #define CCTL1_ TACCTL1_ /* Timer A
Capture/Compare Control 1 */
570 000000 #define CCTL2_ TACCTL2_ /* Timer A
Capture/Compare Control 2 */
571 000000 #define CCR0_ TACCR0_ /* Timer A
Capture/Compare 0 */
572 000000 #define CCR1_ TACCR1_ /* Timer A
Capture/Compare 1 */
573 000000 #define CCR2_ TACCR2_ /* Timer A
Capture/Compare 2 */
574 000000
575 000000 #define TASSEL1 (0x0200u) /* Timer
A clock source select 0 */
576 000000 #define TASSEL0 (0x0100u) /* Timer
A clock source select 1 */
577 000000 #define ID1 (0x0080u) /* Timer
A clock input divider 1 */
578 000000 #define ID0 (0x0040u) /* Timer
A clock input divider 0 */
579 000000 #define MC1 (0x0020u) /* Timer
A mode control 1 */
580 000000 #define MC0 (0x0010u) /* Timer
A mode control 0 */
581 000000 #define TACLR (0x0004u) /* Timer
A counter clear */
582 000000 #define TAIE (0x0002u) /* Timer
A counter interrupt enable */
583 000000 #define TAIFG (0x0001u) /* Timer
A counter interrupt flag */
584 000000
585 000000 #define MC_0 (0*0x10u) /* Timer
A mode control: 0 - Stop */
586 000000 #define MC_1 (1*0x10u) /* Timer
A mode control: 1 - Up to CCR0 */
587 000000 #define MC_2 (2*0x10u) /* Timer
A mode control: 2 - Continous up */
588 000000 #define MC_3 (3*0x10u) /* Timer
A mode control: 3 - Up/Down */
589 000000 #define ID_0 (0*0x40u) /* Timer
A input divider: 0 - /1 */
590 000000 #define ID_1 (1*0x40u) /* Timer
A input divider: 1 - /2 */
591 000000 #define ID_2 (2*0x40u) /* Timer
A input divider: 2 - /4 */
592 000000 #define ID_3 (3*0x40u) /* Timer
A input divider: 3 - /8 */
593 000000 #define TASSEL_0 (0*0x100u) /* Timer
A clock source select: 0 - TACLK */
594 000000 #define TASSEL_1 (1*0x100u) /* Timer
A clock source select: 1 - ACLK */
595 000000 #define TASSEL_2 (2*0x100u) /* Timer
A clock source select: 2 - SMCLK */
596 000000 #define TASSEL_3 (3*0x100u) /* Timer
A clock source select: 3 - INCLK */
597 000000
598 000000 #define CM1 (0x8000u) /*
Capture mode 1 */
599 000000 #define CM0 (0x4000u) /*
Capture mode 0 */
600 000000 #define CCIS1 (0x2000u) /*
Capture input select 1 */
601 000000 #define CCIS0 (0x1000u) /*
Capture input select 0 */
602 000000 #define SCS (0x0800u) /*
Capture sychronize */
603 000000 #define SCCI (0x0400u) /*
Latched capture signal (read) */
604 000000 #define CAP (0x0100u) /*
Capture mode: 1 /Compare mode : 0 */
605 000000 #define OUTMOD2 (0x0080u) /* Output
mode 2 */
606 000000 #define OUTMOD1 (0x0040u) /* Output
mode 1 */
607 000000 #define OUTMOD0 (0x0020u) /* Output
mode 0 */
608 000000 #define CCIE (0x0010u) /*
Capture/compare interrupt enable */
609 000000 #define CCI (0x0008u) /*
Capture input signal (read) */
610 000000 #define OUT (0x0004u) /* PWM
Output signal if output mode 0 */
611 000000 #define COV (0x0002u) /*
Capture/compare overflow flag */
612 000000 #define CCIFG (0x0001u) /*
Capture/compare interrupt flag */
613 000000
614 000000 #define OUTMOD_0 (0*0x20u) /* PWM
output mode: 0 - output only */
615 000000 #define OUTMOD_1 (1*0x20u) /* PWM
output mode: 1 - set */
616 000000 #define OUTMOD_2 (2*0x20u) /* PWM
output mode: 2 - PWM toggle/reset */
617 000000 #define OUTMOD_3 (3*0x20u) /* PWM
output mode: 3 - PWM set/reset */
618 000000 #define OUTMOD_4 (4*0x20u) /* PWM
output mode: 4 - toggle */
619 000000 #define OUTMOD_5 (5*0x20u) /* PWM
output mode: 5 - Reset */
620 000000 #define OUTMOD_6 (6*0x20u) /* PWM
output mode: 6 - PWM toggle/set */
621 000000 #define OUTMOD_7 (7*0x20u) /* PWM
output mode: 7 - PWM reset/set */
622 000000 #define CCIS_0 (0*0x1000u) /*
Capture input select: 0 - CCIxA */
623 000000 #define CCIS_1 (1*0x1000u) /*
Capture input select: 1 - CCIxB */
624 000000 #define CCIS_2 (2*0x1000u) /*
Capture input select: 2 - GND */
625 000000 #define CCIS_3 (3*0x1000u) /*
Capture input select: 3 - Vcc */
626 000000 #define CM_0 (0*0x4000u) /*
Capture mode: 0 - disabled */
627 000000 #define CM_1 (1*0x4000u) /*
Capture mode: 1 - pos. edge */
628 000000 #define CM_2 (2*0x4000u) /*
Capture mode: 1 - neg. edge */
629 000000 #define CM_3 (3*0x4000u) /*
Capture mode: 1 - both edges */
630 000000
631 000000 /* T0_A3IV Definitions */
632 000000 #define TA0IV_NONE (0x0000u) /* No
Interrupt pending */
633 000000 #define TA0IV_TACCR1 (0x0002u) /*
TA0CCR1_CCIFG */
634 000000 #define TA0IV_TACCR2 (0x0004u) /*
TA0CCR2_CCIFG */
635 000000 #define TA0IV_6 (0x0006u) /*
Reserved */
636 000000 #define TA0IV_8 (0x0008u) /*
Reserved */
637 000000 #define TA0IV_TAIFG (0x000Au) /*
TA0IFG */
638 000000
639 000000 /***********************************************
*************
640 000000 * Timer1_A3
641 000000 ************************************************
************/
642 000000 #define __MSP430_HAS_T1A3__ /*
Definition to show that Module is available
*/
643 000000
644 000000 #define TA1IV_ (0x011Eu) /*
Timer1_A3 Interrupt Vector Word */
645 000000 READ_ONLY DEFW( TA1IV , TA1IV_)
646 000000 #define TA1CTL_ (0x0180u) /*
Timer1_A3 Control */
647 000000 DEFW( TA1CTL , TA1CTL_)
648 000000 #define TA1CCTL0_ (0x0182u) /*
Timer1_A3 Capture/Compare Control 0 */
649 000000 DEFW( TA1CCTL0 , TA1CCTL0_)
650 000000 #define TA1CCTL1_ (0x0184u) /*
Timer1_A3 Capture/Compare Control 1 */
651 000000 DEFW( TA1CCTL1 , TA1CCTL1_)
652 000000 #define TA1CCTL2_ (0x0186u) /*
Timer1_A3 Capture/Compare Control 2 */
653 000000 DEFW( TA1CCTL2 , TA1CCTL2_)
654 000000 #define TA1R_ (0x0190u) /*
Timer1_A3 */
655 000000 DEFW( TA1R , TA1R_)
656 000000 #define TA1CCR0_ (0x0192u) /*
Timer1_A3 Capture/Compare 0 */
657 000000 DEFW( TA1CCR0 , TA1CCR0_)
658 000000 #define TA1CCR1_ (0x0194u) /*
Timer1_A3 Capture/Compare 1 */
659 000000 DEFW( TA1CCR1 , TA1CCR1_)
660 000000 #define TA1CCR2_ (0x0196u) /*
Timer1_A3 Capture/Compare 2 */
661 000000 DEFW( TA1CCR2 , TA1CCR2_)
662 000000
663 000000 /* Bits are already defined within the Timer0_Ax
*/
664 000000
665 000000 /* T1_A3IV Definitions */
666 000000 #define TA1IV_NONE (0x0000u) /* No
Interrupt pending */
667 000000 #define TA1IV_TACCR1 (0x0002u) /*
TA1CCR1_CCIFG */
668 000000 #define TA1IV_TACCR2 (0x0004u) /*
TA1CCR2_CCIFG */
669 000000 #define TA1IV_TAIFG (0x000Au) /*
TA1IFG */
670 000000
671 000000 /***********************************************
*************
672 000000 * USCI
673 000000 ************************************************
************/
674 000000 #define __MSP430_HAS_USCI__ /*
Definition to show that Module is available
*/
675 000000
676 000000 #define UCA0CTL0_ (0x0060u) /* USCI
A0 Control Register 0 */
677 000000 DEFC( UCA0CTL0 , UCA0CTL0_)
678 000000 #define UCA0CTL1_ (0x0061u) /* USCI
A0 Control Register 1 */
679 000000 DEFC( UCA0CTL1 , UCA0CTL1_)
680 000000 #define UCA0BR0_ (0x0062u) /* USCI
A0 Baud Rate 0 */
681 000000 DEFC( UCA0BR0 , UCA0BR0_)
682 000000 #define UCA0BR1_ (0x0063u) /* USCI
A0 Baud Rate 1 */
683 000000 DEFC( UCA0BR1 , UCA0BR1_)
684 000000 #define UCA0MCTL_ (0x0064u) /* USCI
A0 Modulation Control */
685 000000 DEFC( UCA0MCTL , UCA0MCTL_)
686 000000 #define UCA0STAT_ (0x0065u) /* USCI
A0 Status Register */
687 000000 DEFC( UCA0STAT , UCA0STAT_)
688 000000 #define UCA0RXBUF_ (0x0066u) /* USCI
A0 Receive Buffer */
689 000000 READ_ONLY DEFC( UCA0RXBUF , UCA0RXBUF_)
690 000000 #define UCA0TXBUF_ (0x0067u) /* USCI
A0 Transmit Buffer */
691 000000 DEFC( UCA0TXBUF , UCA0TXBUF_)
692 000000 #define UCA0ABCTL_ (0x005Du) /* USCI
A0 LIN Control */
693 000000 DEFC( UCA0ABCTL , UCA0ABCTL_)
694 000000 #define UCA0IRTCTL_ (0x005Eu) /* USCI
A0 IrDA Transmit Control */
695 000000 DEFC( UCA0IRTCTL , UCA0IRTCTL_)
696 000000 #define UCA0IRRCTL_ (0x005Fu) /* USCI
A0 IrDA Receive Control */
697 000000 DEFC( UCA0IRRCTL , UCA0IRRCTL_)
698 000000
699 000000
700 000000
701 000000 #define UCB0CTL0_ (0x0068u) /* USCI
B0 Control Register 0 */
702 000000 DEFC( UCB0CTL0 , UCB0CTL0_)
703 000000 #define UCB0CTL1_ (0x0069u) /* USCI
B0 Control Register 1 */
704 000000 DEFC( UCB0CTL1 , UCB0CTL1_)
705 000000 #define UCB0BR0_ (0x006Au) /* USCI
B0 Baud Rate 0 */
706 000000 DEFC( UCB0BR0 , UCB0BR0_)
707 000000 #define UCB0BR1_ (0x006Bu) /* USCI
B0 Baud Rate 1 */
708 000000 DEFC( UCB0BR1 , UCB0BR1_)
709 000000 #define UCB0I2CIE_ (0x006Cu) /* USCI
B0 I2C Interrupt Enable Register */
710 000000 DEFC( UCB0I2CIE , UCB0I2CIE_)
711 000000 #define UCB0STAT_ (0x006Du) /* USCI
B0 Status Register */
712 000000 DEFC( UCB0STAT , UCB0STAT_)
713 000000 #define UCB0RXBUF_ (0x006Eu) /* USCI
B0 Receive Buffer */
714 000000 READ_ONLY DEFC( UCB0RXBUF , UCB0RXBUF_)
715 000000 #define UCB0TXBUF_ (0x006Fu) /* USCI
B0 Transmit Buffer */
716 000000 DEFC( UCB0TXBUF , UCB0TXBUF_)
717 000000 #define UCB0I2COA_ (0x0118u) /* USCI
B0 I2C Own Address */
718 000000 DEFW( UCB0I2COA , UCB0I2COA_)
719 000000 #define UCB0I2CSA_ (0x011Au) /* USCI
B0 I2C Slave Address */
720 000000 DEFW( UCB0I2CSA , UCB0I2CSA_)
721 000000
722 000000 // UART-Mode Bits
723 000000 #define UCPEN (0x80) /* Async.
Mode: Parity enable */
724 000000 #define UCPAR (0x40) /* Async.
Mode: Parity 0:odd / 1:even */
725 000000 #define UCMSB (0x20) /* Async.
Mode: MSB first 0:LSB / 1:MSB */
726 000000 #define UC7BIT (0x10) /* Async.
Mode: Data Bits 0:8-bits / 1:7-bits */
727 000000 #define UCSPB (0x08) /* Async.
Mode: Stop Bits 0:one / 1: two */
728 000000 #define UCMODE1 (0x04) /* Async.
Mode: USCI Mode 1 */
729 000000 #define UCMODE0 (0x02) /* Async.
Mode: USCI Mode 0 */
730 000000 #define UCSYNC (0x01) /*
Sync-Mode 0:UART-Mode / 1:SPI-Mode */
731 000000
732 000000 // SPI-Mode Bits
733 000000 #define UCCKPH (0x80) /* Sync.
Mode: Clock Phase */
734 000000 #define UCCKPL (0x40) /* Sync.
Mode: Clock Polarity */
735 000000 #define UCMST (0x08) /* Sync.
Mode: Master Select */
736 000000
737 000000 // I2C-Mode Bits
738 000000 #define UCA10 (0x80) /* 10-bit
Address Mode */
739 000000 #define UCSLA10 (0x40) /* 10-bit
Slave Address Mode */
740 000000 #define UCMM (0x20) /*
Multi-Master Environment */
741 000000 //#define res (0x10) /*
reserved */
742 000000 #define UCMODE_0 (0x00) /* Sync.
Mode: USCI Mode: 0 */
743 000000 #define UCMODE_1 (0x02) /* Sync.
Mode: USCI Mode: 1 */
744 000000 #define UCMODE_2 (0x04) /* Sync.
Mode: USCI Mode: 2 */
745 000000 #define UCMODE_3 (0x06) /* Sync.
Mode: USCI Mode: 3 */
746 000000
747 000000 // UART-Mode Bits
748 000000 #define UCSSEL1 (0x80) /* USCI 0
Clock Source Select 1 */
749 000000 #define UCSSEL0 (0x40) /* USCI 0
Clock Source Select 0 */
750 000000 #define UCRXEIE (0x20) /* RX
Error interrupt enable */
751 000000 #define UCBRKIE (0x10) /* Break
interrupt enable */
752 000000 #define UCDORM (0x08) /* Dormant
(Sleep) Mode */
753 000000 #define UCTXADDR (0x04) /* Send
next Data as Address */
754 000000 #define UCTXBRK (0x02) /* Send
next Data as Break */
755 000000 #define UCSWRST (0x01) /* USCI
Software Reset */
756 000000
757 000000 // SPI-Mode Bits
758 000000 //#define res (0x20) /*
reserved */
759 000000 //#define res (0x10) /*
reserved */
760 000000 //#define res (0x08) /*
reserved */
761 000000 //#define res (0x04) /*
reserved */
762 000000 //#define res (0x02) /*
reserved */
763 000000
764 000000 // I2C-Mode Bits
765 000000 //#define res (0x20) /*
reserved */
766 000000 #define UCTR (0x10) /*
Transmit/Receive Select/Flag */
767 000000 #define UCTXNACK (0x08) /*
Transmit NACK */
768 000000 #define UCTXSTP (0x04) /*
Transmit STOP */
769 000000 #define UCTXSTT (0x02) /*
Transmit START */
770 000000 #define UCSSEL_0 (0x00) /* USCI 0
Clock Source: 0 */
771 000000 #define UCSSEL_1 (0x40) /* USCI 0
Clock Source: 1 */
772 000000 #define UCSSEL_2 (0x80) /* USCI 0
Clock Source: 2 */
773 000000 #define UCSSEL_3 (0xC0) /* USCI 0
Clock Source: 3 */
774 000000
775 000000 #define UCBRF3 (0x80) /* USCI
First Stage Modulation Select 3 */
776 000000 #define UCBRF2 (0x40) /* USCI
First Stage Modulation Select 2 */
777 000000 #define UCBRF1 (0x20) /* USCI
First Stage Modulation Select 1 */
778 000000 #define UCBRF0 (0x10) /* USCI
First Stage Modulation Select 0 */
779 000000 #define UCBRS2 (0x08) /* USCI
Second Stage Modulation Select 2 */
780 000000 #define UCBRS1 (0x04) /* USCI
Second Stage Modulation Select 1 */
781 000000 #define UCBRS0 (0x02) /* USCI
Second Stage Modulation Select 0 */
782 000000 #define UCOS16 (0x01) /* USCI
16-times Oversampling enable */
783 000000
784 000000 #define UCBRF_0 (0x00) /* USCI
First Stage Modulation: 0 */
785 000000 #define UCBRF_1 (0x10) /* USCI
First Stage Modulation: 1 */
786 000000 #define UCBRF_2 (0x20) /* USCI
First Stage Modulation: 2 */
787 000000 #define UCBRF_3 (0x30) /* USCI
First Stage Modulation: 3 */
788 000000 #define UCBRF_4 (0x40) /* USCI
First Stage Modulation: 4 */
789 000000 #define UCBRF_5 (0x50) /* USCI
First Stage Modulation: 5 */
790 000000 #define UCBRF_6 (0x60) /* USCI
First Stage Modulation: 6 */
791 000000 #define UCBRF_7 (0x70) /* USCI
First Stage Modulation: 7 */
792 000000 #define UCBRF_8 (0x80) /* USCI
First Stage Modulation: 8 */
793 000000 #define UCBRF_9 (0x90) /* USCI
First Stage Modulation: 9 */
794 000000 #define UCBRF_10 (0xA0) /* USCI
First Stage Modulation: A */
795 000000 #define UCBRF_11 (0xB0) /* USCI
First Stage Modulation: B */
796 000000 #define UCBRF_12 (0xC0) /* USCI
First Stage Modulation: C */
797 000000 #define UCBRF_13 (0xD0) /* USCI
First Stage Modulation: D */
798 000000 #define UCBRF_14 (0xE0) /* USCI
First Stage Modulation: E */
799 000000 #define UCBRF_15 (0xF0) /* USCI
First Stage Modulation: F */
800 000000
801 000000 #define UCBRS_0 (0x00) /* USCI
Second Stage Modulation: 0 */
802 000000 #define UCBRS_1 (0x02) /* USCI
Second Stage Modulation: 1 */
803 000000 #define UCBRS_2 (0x04) /* USCI
Second Stage Modulation: 2 */
804 000000 #define UCBRS_3 (0x06) /* USCI
Second Stage Modulation: 3 */
805 000000 #define UCBRS_4 (0x08) /* USCI
Second Stage Modulation: 4 */
806 000000 #define UCBRS_5 (0x0A) /* USCI
Second Stage Modulation: 5 */
807 000000 #define UCBRS_6 (0x0C) /* USCI
Second Stage Modulation: 6 */
808 000000 #define UCBRS_7 (0x0E) /* USCI
Second Stage Modulation: 7 */
809 000000
810 000000 #define UCLISTEN (0x80) /* USCI
Listen mode */
811 000000 #define UCFE (0x40) /* USCI
Frame Error Flag */
812 000000 #define UCOE (0x20) /* USCI
Overrun Error Flag */
813 000000 #define UCPE (0x10) /* USCI
Parity Error Flag */
814 000000 #define UCBRK (0x08) /* USCI
Break received */
815 000000 #define UCRXERR (0x04) /* USCI RX
Error Flag */
816 000000 #define UCADDR (0x02) /* USCI
Address received Flag */
817 000000 #define UCBUSY (0x01) /* USCI
Busy Flag */
818 000000 #define UCIDLE (0x02) /* USCI
Idle line detected Flag */
819 000000
820 000000 //#define res (0x80) /*
reserved */
821 000000 //#define res (0x40) /*
reserved */
822 000000 //#define res (0x20) /*
reserved */
823 000000 //#define res (0x10) /*
reserved */
824 000000 #define UCNACKIE (0x08) /* NACK
Condition interrupt enable */
825 000000 #define UCSTPIE (0x04) /* STOP
Condition interrupt enable */
826 000000 #define UCSTTIE (0x02) /* START
Condition interrupt enable */
827 000000 #define UCALIE (0x01) /*
Arbitration Lost interrupt enable */
828 000000
829 000000 #define UCSCLLOW (0x40) /* SCL low
*/
830 000000 #define UCGC (0x20) /* General
Call address received Flag */
831 000000 #define UCBBUSY (0x10) /* Bus
Busy Flag */
832 000000 #define UCNACKIFG (0x08) /* NAK
Condition interrupt Flag */
833 000000 #define UCSTPIFG (0x04) /* STOP
Condition interrupt Flag */
834 000000 #define UCSTTIFG (0x02) /* START
Condition interrupt Flag */
835 000000 #define UCALIFG (0x01) /*
Arbitration Lost interrupt Flag */
836 000000
837 000000 #define UCIRTXPL5 (0x80) /* IRDA
Transmit Pulse Length 5 */
838 000000 #define UCIRTXPL4 (0x40) /* IRDA
Transmit Pulse Length 4 */
839 000000 #define UCIRTXPL3 (0x20) /* IRDA
Transmit Pulse Length 3 */
840 000000 #define UCIRTXPL2 (0x10) /* IRDA
Transmit Pulse Length 2 */
841 000000 #define UCIRTXPL1 (0x08) /* IRDA
Transmit Pulse Length 1 */
842 000000 #define UCIRTXPL0 (0x04) /* IRDA
Transmit Pulse Length 0 */
843 000000 #define UCIRTXCLK (0x02) /* IRDA
Transmit Pulse Clock Select */
844 000000 #define UCIREN (0x01) /* IRDA
Encoder/Decoder enable */
845 000000
846 000000 #define UCIRRXFL5 (0x80) /* IRDA
Receive Filter Length 5 */
847 000000 #define UCIRRXFL4 (0x40) /* IRDA
Receive Filter Length 4 */
848 000000 #define UCIRRXFL3 (0x20) /* IRDA
Receive Filter Length 3 */
849 000000 #define UCIRRXFL2 (0x10) /* IRDA
Receive Filter Length 2 */
850 000000 #define UCIRRXFL1 (0x08) /* IRDA
Receive Filter Length 1 */
851 000000 #define UCIRRXFL0 (0x04) /* IRDA
Receive Filter Length 0 */
852 000000 #define UCIRRXPL (0x02) /* IRDA
Receive Input Polarity */
853 000000 #define UCIRRXFE (0x01) /* IRDA
Receive Filter enable */
854 000000
855 000000 //#define res (0x80) /*
reserved */
856 000000 //#define res (0x40) /*
reserved */
857 000000 #define UCDELIM1 (0x20) /* Break
Sync Delimiter 1 */
858 000000 #define UCDELIM0 (0x10) /* Break
Sync Delimiter 0 */
859 000000 #define UCSTOE (0x08) /*
Sync-Field Timeout error */
860 000000 #define UCBTOE (0x04) /* Break
Timeout error */
861 000000 //#define res (0x02) /*
reserved */
862 000000 #define UCABDEN (0x01) /* Auto
Baud Rate detect enable */
863 000000
864 000000 #define UCGCEN (0x8000u) /* I2C
General Call enable */
865 000000 #define UCOA9 (0x0200u) /* I2C
Own Address 9 */
866 000000 #define UCOA8 (0x0100u) /* I2C
Own Address 8 */
867 000000 #define UCOA7 (0x0080u) /* I2C
Own Address 7 */
868 000000 #define UCOA6 (0x0040u) /* I2C
Own Address 6 */
869 000000 #define UCOA5 (0x0020u) /* I2C
Own Address 5 */
870 000000 #define UCOA4 (0x0010u) /* I2C
Own Address 4 */
871 000000 #define UCOA3 (0x0008u) /* I2C
Own Address 3 */
872 000000 #define UCOA2 (0x0004u) /* I2C
Own Address 2 */
873 000000 #define UCOA1 (0x0002u) /* I2C
Own Address 1 */
874 000000 #define UCOA0 (0x0001u) /* I2C
Own Address 0 */
875 000000
876 000000 #define UCSA9 (0x0200u) /* I2C
Slave Address 9 */
877 000000 #define UCSA8 (0x0100u) /* I2C
Slave Address 8 */
878 000000 #define UCSA7 (0x0080u) /* I2C
Slave Address 7 */
879 000000 #define UCSA6 (0x0040u) /* I2C
Slave Address 6 */
880 000000 #define UCSA5 (0x0020u) /* I2C
Slave Address 5 */
881 000000 #define UCSA4 (0x0010u) /* I2C
Slave Address 4 */
882 000000 #define UCSA3 (0x0008u) /* I2C
Slave Address 3 */
883 000000 #define UCSA2 (0x0004u) /* I2C
Slave Address 2 */
884 000000 #define UCSA1 (0x0002u) /* I2C
Slave Address 1 */
885 000000 #define UCSA0 (0x0001u) /* I2C
Slave Address 0 */
886 000000
887 000000 /***********************************************
*************
888 000000 * WATCHDOG TIMER
889 000000 ************************************************
************/
890 000000 #define __MSP430_HAS_WDT__ /*
Definition to show that Module is available
*/
891 000000
892 000000 #define WDTCTL_ (0x0120u) /*
Watchdog Timer Control */
893 000000 DEFW( WDTCTL , WDTCTL_)
894 000000 /* The bit names have been prefixed with "WDT"
*/
895 000000 #define WDTIS0 (0x0001u)
896 000000 #define WDTIS1 (0x0002u)
897 000000 #define WDTSSEL (0x0004u)
898 000000 #define WDTCNTCL (0x0008u)
899 000000 #define WDTTMSEL (0x0010u)
900 000000 #define WDTNMI (0x0020u)
901 000000 #define WDTNMIES (0x0040u)
902 000000 #define WDTHOLD (0x0080u)
903 000000
904 000000 #define WDTPW (0x5A00u)
905 000000
906 000000 /* WDT-interval times [1ms] coded with Bits 0-2
*/
907 000000 /* WDT is clocked by fSMCLK (assumed 1MHz)
*/
908 000000 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTC
NTCL) /* 32ms interval
(default) */
909 000000 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTIS0) /* 8ms "
*/
910 000000 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTIS1) /* 0.5ms "
*/
911 000000 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTIS1+WDTIS0) /* 0.064ms "
*/
912 000000 /* WDT is clocked by fACLK (assumed 32KHz)
*/
913 000000 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTSSEL) /* 1000ms "
*/
914 000000 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTSSEL+WDTIS0) /* 250ms "
*/
915 000000 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTSSEL+WDTIS1) /* 16ms "
*/
916 000000 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTC
NTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms "
*/
917 000000 /* Watchdog mode -> reset after expired time
*/
918 000000 /* WDT is clocked by fSMCLK (assumed 1MHz)
*/
919 000000 #define WDT_MRST_32 (WDTPW+WDTCNTCL)
/* 32ms interval
(default) */
920 000000 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTI
S0) /* 8ms "
*/
921 000000 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTI
S1) /* 0.5ms "
*/
922 000000 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTI
S1+WDTIS0) /* 0.064ms "
*/
923 000000 /* WDT is clocked by fACLK (assumed 32KHz)
*/
924 000000 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTS
SEL) /* 1000ms "
*/
925 000000 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTS
SEL+WDTIS0) /* 250ms "
*/
926 000000 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTS
SEL+WDTIS1) /* 16ms "
*/
927 000000 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTS
SEL+WDTIS1+WDTIS0) /* 1.9ms "
*/
928 000000
929 000000 /* INTERRUPT CONTROL */
930 000000 /* These two bits are defined in the Special
Function Registers */
931 000000 /* #define WDTIE 0x01 */
932 000000 /* #define WDTIFG 0x01 */
933 000000
934 000000 /***********************************************
*************
935 000000 * Calibration Data in Info Mem
936 000000 ************************************************
************/
937 000000
938 000000 #ifndef __DisableCalData
939 000000
940 000000 #define CALDCO_16MHZ_ (0x10F8u) /*
DCOCTL Calibration Data for 16MHz */
941 000000 READ_ONLY DEFC( CALDCO_16MHZ , CALDCO_16MHZ_
)
942 000000 #define CALBC1_16MHZ_ (0x10F9u) /*
BCSCTL1 Calibration Data for 16MHz */
943 000000 READ_ONLY DEFC( CALBC1_16MHZ , CALBC1_16MHZ_
)
944 000000 #define CALDCO_12MHZ_ (0x10FAu) /*
DCOCTL Calibration Data for 12MHz */
945 000000 READ_ONLY DEFC( CALDCO_12MHZ , CALDCO_12MHZ_
)
946 000000 #define CALBC1_12MHZ_ (0x10FBu) /*
BCSCTL1 Calibration Data for 12MHz */
947 000000 READ_ONLY DEFC( CALBC1_12MHZ , CALBC1_12MHZ_
)
948 000000 #define CALDCO_8MHZ_ (0x10FCu) /*
DCOCTL Calibration Data for 8MHz */
949 000000 READ_ONLY DEFC( CALDCO_8MHZ , CALDCO_8MHZ_)
950 000000 #define CALBC1_8MHZ_ (0x10FDu) /*
BCSCTL1 Calibration Data for 8MHz */
951 000000 READ_ONLY DEFC( CALBC1_8MHZ , CALBC1_8MHZ_)
952 000000 #define CALDCO_1MHZ_ (0x10FEu) /*
DCOCTL Calibration Data for 1MHz */
953 000000 READ_ONLY DEFC( CALDCO_1MHZ , CALDCO_1MHZ_)
954 000000 #define CALBC1_1MHZ_ (0x10FFu) /*
BCSCTL1 Calibration Data for 1MHz */
955 000000 READ_ONLY DEFC( CALBC1_1MHZ , CALBC1_1MHZ_)
956 000000
957 000000 #endif /* #ifndef __DisableCalData */
958 000000
959 000000 /***********************************************
*************
960 000000 * Interrupt Vectors (offset from 0xFFE0)
961 000000 ************************************************
************/
962 000000
963 000000 #define PORT1_VECTOR (2 * 2u) /* 0xFFE4
Port 1 */
964 000000 #define PORT2_VECTOR (3 * 2u) /* 0xFFE6
Port 2 */
965 000000 #define ADC10_VECTOR (5 * 2u) /* 0xFFEA
ADC10 */
966 000000 #define USCIAB0TX_VECTOR (6 * 2u) /* 0xFFEC
USCI A0/B0 Transmit */
967 000000 #define USCIAB0RX_VECTOR (7 * 2u) /* 0xFFEE
USCI A0/B0 Receive */
968 000000 #define TIMER0_A1_VECTOR (8 * 2u) /* 0xFFF0
Timer0)A CC1, TA0 */
969 000000 #define TIMER0_A0_VECTOR (9 * 2u) /* 0xFFF2
Timer0_A CC0 */
970 000000 #define WDT_VECTOR (10 * 2u) /* 0xFFF4
Watchdog Timer */
971 000000 #define COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6
Comparator A */
972 000000 #define TIMER1_A1_VECTOR (12 * 2u) /* 0xFFF8
Timer1_A CC1-4, TA1 */
973 000000 #define TIMER1_A0_VECTOR (13 * 2u) /* 0xFFFA
Timer1_A CC0 */
974 000000 #define NMI_VECTOR (14 * 2u) /* 0xFFFC
Non-maskable */
975 000000 #define RESET_VECTOR (15 * 2u) /* 0xFFFE
Reset [Highest Priority] */
976 000000
977 000000 /***********************************************
*************
978 000000 * End of Modules
979 000000 ************************************************
************/
980 000000 #pragma language=default
981 000000
982 000000 #endif /* #ifndef __MSP430G2553 */
983 000000
986 000000
987 000000 #elif defined (__MSP430G2203__)
988 000000 #include "msp430g2203.h"
990 000000 #elif defined (__MSP430G2303__)
991 000000 #include "msp430g2303.h"
993 000000 #elif defined (__MSP430G2403__)
994 000000 #include "msp430g2403.h"
996 000000 #elif defined (__MSP430G2233__)
997 000000 #include "msp430g2233.h"
999 000000 #elif defined (__MSP430G2333__)
1000 000000 #include "msp430g2333.h"
1002 000000 #elif defined (__MSP430G2433__)
1003 000000 #include "msp430g2433.h"
1005 000000 #elif defined (__MSP430G2533__)
1006 000000 #include "msp430g2533.h"
1008 000000 #elif defined (__MSP430BT5190__)
1009 000000 #include "msp430bt5190.h"
1014 000000 #elif defined (__MSP430GENERIC__)
1015 000000 #error "msp430 generic device does not have a
default include file"
1017 000000 #elif defined (__MSP430XGENERIC__)
1018 000000 #error "msp430X generic device does not have a
default include file"
1024 000000 #else
1025 000000 #error "Failed to match a default include
file"
1026 000000 #endif
1027 000000
1028 000000 #endif /* #ifndef __msp430 */
1029 000000
29 000000 #include "CF430G2553forth.h" ;
header macros and register defs
1 000000 ; ----------------------------------------------
------------------------
2 000000 ; CF430G2553 is a Forth based on CamelForth
3 000000 ; for the Texas Instruments MSP430
4 000000 ;
5 000000 ; This program is free software; you can
redistribute it and/or modify
6 000000 ; it under the terms of the GNU General Public
License as published by
7 000000 ; the Free Software Foundation; either version 3
of the License, or
8 000000 ; (at your option) any later version.
9 000000 ;
10 000000 ; This program is distributed in the hope that
it will be useful,
11 000000 ; but WITHOUT ANY WARRANTY; without even the
implied warranty of
12 000000 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the
13 000000 ; GNU General Public License for more details.
14 000000 ;
15 000000 ; You should have received a copy of the GNU
General Public License
16 000000 ; along with this program. If not, see
.
17 000000 ;
18 000000 ; See LICENSE TERMS in Brads file readme.txt as
well.
19 000000
20 000000 ; ----------------------------------------------
------------------------
21 000000 ; CF430G2553forth.h: - Register, Model, Macro
declarations - MSP430G2553
22 000000 ; ----------------------------------------------
------------------------
23 000000
24 000000 // ; FORTH MEMORY USAGE
25 000000 // ; for Flash memory operations - this includes
information and main
26 000000 // ; ROM, but not the main ROM used by the
kernel (above E000h)
27 000000 #define INFOSTART (0x1000) // ok mk
28 000000 #define INFOEND (0x10FF) // ok mk
29 000000 #define RAMSTART (0x0200) // ok mk
30 000000 #define RAMEND (0x0400) // ok mk
31 000000 #define FLASHSTART (0xC000) // ok mk
32 000000 #define FLASHEND (0xDFFF) // ok mk
33 000000 #define MAINSEG (512) // wozu ?? mk
34 000000 #define INFOSEG (128) // ?? mk
35 000000
36 000000 // ; FORTH REGISTER USAGE
37 000000
38 000000 // ; Forth virtual machine
39 000000 #define RSP SP
40 000000 #define PSP R4
41 000000 #define IP R5
42 000000 #define W R6
43 000000 #define TOS R7
44 000000
45 000000 // ; Loop parameters in registers
46 000000 #define INDEX R8
47 000000 #define LIMIT R9
48 000000
49 000000 // ; Scratch registers
50 000000 #define X R10
51 000000 #define Y R11
52 000000 #define Q R12
53 000000 #define T R13
54 000000
55 000000 // ; T.I. Integer Subroutines Definitions
56 000000 #define IROP1 TOS
57 000000 #define IROP2L R10
58 000000 #define IROP2M R11
59 000000 #define IRACL R12
60 000000 #define IRACM R13
61 000000 #define IRBT W
62 000000
63 000000 // ; INDIRECT-THREADED NEXT
64 000000
69 000000
70 000000 // ; BRANCH DESTINATION (RELATIVE BRANCH)
71 000000 // ; For relative branch addresses, i.e., a
branch is ADD @IP,IP
72 000000
76 000000
77 000000 // ; HEADER CONSTRUCTION MACROS
78 000000
93 000000
102 000000
111 000000
126 000000
30 000000
31 000000 EXTERN UP,UAREA,PADAREA,LSTACK,PSTACK,R
STACK
32 000000 EXTERN TIBAREA,RAMDICT,ROMDICT
33 000000 EXTERN TIB_SIZE,UAREA_SIZE,nullirq
34 000000
35 000000 RSEG CODE ; place
program in 'CODE' segment
36 000000
37 000000 link SET 0 ; initial dictionary
link
38 000000
39 000000 version:
40 000000 1F DB (verend-ver0)
41 000001 434634333047*ver0: DB 'CF430G2553 D0.34 ',__date__,'|' ; D
= debug version
42 00001F 00 EVEN
43 000020 verend:
44 000020
45 000020 ; ----------------------------------------------
------------------------
46 000020 ; INTERPRETER LOGIC
47 000020 ; ITC NEXT is defined as
48 000020 ; MOV @IP+,W ; 2 fetch word address
into W
49 000020 ; MOV @W+,PC ; 2 fetch code address
into PC, W=PFA
50 000020
51 000020 ;C EXECUTE i*x xt -- j*x execute Forth
word
52 000020 ;C at 'xt'
53 000020 HEADER EXECUTE,7,'EXECUTE',DOCODE
54 00002E 0647 MOV TOS,W ; 1 put word address
into W
55 000030 3744 MOV @PSP+,TOS ; 2 fetch new TOS
56 000032 3046 MOV @W+,PC ; 2 fetch code address
into PC, W=PFA
57 000034
58 000034 ;Z lit -- x fetch inline literal to
stack
59 000034 ; This is the primtive compiled by LITERAL.
60 000034 HEADER lit,3,'lit',DOCODE
61 00003E 2483 SUB #2,PSP ; 1 push old TOS..
62 000040 84470000 MOV TOS,0(PSP) ; 4 ..onto stack
63 000044 3745 MOV @IP+,TOS ; 2 fetch new TOS
value
64 000046 NEXT ; 4
65 00004A
66 00004A ;C EXIT -- exit a colon
definition
67 00004A HEADER EXIT,4,'EXIT',DOCODE
68 000054 3541 MOV @RSP+,IP ; 2 pop old IP from
return stack
69 000056 NEXT ; 4
70 00005A
71 00005A ; ----------------------------------------------
------------------------
72 00005A ; DEFINING WORDS - ROMable ITC model
73 00005A
74 00005A ; DOCOLON enters a new high-level thread (colon
definition.)
75 00005A ; (internal code fragment, not a Forth
word)
76 000000 PUBLIC DOCOLON
77 00005A DOCOLON:
78 00005A 0512 PUSH IP ; 3 save old IP on
return stack
79 00005C 0546 MOV W,IP ; 1 set new IP to
PFA
80 00005E NEXT ; 4
81 000062
82 000062 ;C VARIABLE -- define a Forth
VARIABLE
83 000062 ; CREATE CELL ALLOT ;
84 000062 ; Action of ROMable variable is the same as
CREATE; it builds a
85 000062 ; constant holding the RAM address. See CREATE
in hilvl430.s43.
86 000062 HEADER VARIABLE,8,'VARIABLE',DOCOLON
87 000070 ............* DW CREATE,CELL,ALLOT,EXIT
88 000078
89 000078 ;C CONSTANT -- define a Forth
constant
90 000078 ; (machine code fragment)
92 000078 ; Note that the constant is stored in Code
space.
93 000078 HEADER CONSTANT,8,'CONSTANT',DOCOLON
94 000086 ............ DW BUILDS,ICOMMA,XDOES
95 00008C ; DOCON, code action of CONSTANT,
96 00008C ; entered with W=Parameter Field Adrs
97 00008C ; This is also the action of VARIABLE (Harvard
model)
98 00008C ; This is also the action of CREATE (Harvard
model)
99 000000 PUBLIC DOCON
100 000000 PUBLIC docreate
101 000000 PUBLIC DOVAR
102 00008C docreate: ; -- a-addr ; ROMable CREATE fetches
address from PFA
103 00008C DOVAR: ; -- a-addr ; ROMable VARIABLE
fetches address from PFA
104 00008C DOCON: ; -- x ; CONSTANT fetches cell
from PFA to TOS
105 00008C 2483 SUB #2,PSP ; make room on
stack
106 00008E 84470000 MOV TOS,0(PSP)
107 000092 2746 MOV @W,TOS ; fetch from parameter
field to TOS
108 000094 NEXT
109 000098
110 000098 ; DOCREATE's action is for a table in RAM.
111 000098 ; DOROM is the code action for a table in
ROM;
112 000098 ; it returns the address of the parameter
field.
113 000000 PUBLIC DOROM
114 000098 DOROM: ; -- a-addr ; Table in ROM: get PFA
into TOS
115 000098 2483 SUB #2,PSP
116 00009A 84470000 MOV TOS,0(PSP)
117 00009E 0746 MOV W,TOS
118 0000A0 NEXT
119 0000A4
120 0000A4 ;Z USER n -- define user variable
'n'
121 0000A4 ; (machine code fragment)
Flashable model
122 0000A4 HEADER USER,4,'USER',DOCOLON
123 0000AE ............ DW BUILDS,ICOMMA,XDOES
124 000000 PUBLIC DOUSER
125 0000B4 DOUSER: ; -- a-addr ; add constant to User
Pointer, result in TOS
126 0000B4 2483 SUB #2,PSP
127 0000B6 84470000 MOV TOS,0(PSP)
128 0000BA 2746 MOV @W,TOS
129 0000BC 1752.... ADD &UP,TOS
130 0000C0 NEXT
131 0000C4
132 0000C4 ; DOALIAS used to build a word which performs
the action of
133 0000C4 ; another word. Its action is to fetch the
"alias" CFA from
134 0000C4 ; the parameter field, and execute that, e.g.
DOES> I@ EXECUTE ;
135 0000C4 ; This is currently used only within the Forth
kernel.
136 000000 PUBLIC DOALIAS
137 0000C4 DOALIAS: ; -- ; fetch CFA of word to
execute
138 0000C4 2646 MOV @W,W ; 2 fetch from parameter
field to W
139 0000C6 3046 MOV @W+,PC ; 2 fetch code address
into PC, W=PFA
140 0000C8
141 0000C8 ; DODOES is the code action of a DOES> clause.
For ITC Forth:
142 0000C8 ; defined word: CFA: doescode
143 0000C8 ; PFA: parameter field
144 0000C8 ;
145 0000C8 ; doescode: MOV #DODOES,PC ; 16-bit direct
jump, in two cells
146 0000C8 ; high-level thread
147 0000C8 ;
148 0000C8 ; Note that we use JMP DODOES instead of CALL
#DODOES because we can
149 0000C8 ; efficiently obtain the thread address. DODOES
is entered with W=PFA.
150 0000C8 ; It enters the high-level thread with the
address of the parameter
151 0000C8 ; field on top of stack.
152 0000C8
153 000000 PUBLIC dodoes
154 0000C8 dodoes: ; -- a-addr ; 3 for MOV #DODOES,PC
155 0000C8 2483 SUB #2,PSP ; 1 make room on
stack
156 0000CA 84470000 MOV TOS,0(PSP) ; 4
157 0000CE 0746 MOV W,TOS ; 1 put defined word's
PFA in TOS
158 0000D0 0512 PUSH IP ; 3 save old IP on
return stack
159 0000D2 1546FEFF MOV -2(W),IP ; 3 fetch adrs of
doescode from defined
word
160 0000D6 2552 ADD #4,IP ; 1 skip MOV instruction
to get thread
adrs
161 0000D8 NEXT ; 4
162 0000DC
163 0000DC ; OPTION 1 ; OPTION 2
164 0000DC ; MOV #DODOES,PC 3 ; CALL #DODOES
5
165 0000DC ; ... ; ...
166 0000DC ; PUSH IP 3 ; POP W
2
167 0000DC ; MOVE -2(W),IP 3 ; PUSH IP
3
168 0000DC ; ADD #4,IP 1 ; MOV W,IP
1
169 0000DC
170 0000DC
171 0000DC ; ----------------------------------------------
------------------------
172 0000DC ; STACK OPERATIONS
173 0000DC
174 0000DC ;C DUP x -- x x duplicate top of
stack
175 0000DC HEADER DUP,3,'DUP',DOCODE
176 0000E6 2483 PUSHTOS: SUB #2,PSP ; 1 push old
TOS..
177 0000E8 84470000 MOV TOS,0(PSP) ; 4 ..onto
stack
178 0000EC NEXT ; 4
179 0000F0
180 0000F0 ;C ?DUP x -- 0 | x x DUP if nonzero
181 0000F0 HEADER QDUP,4,'?DUP',DOCODE
182 0000FA 0793 CMP #0,TOS ; 1 test for
TOS nonzero
183 0000FC F423 JNZ PUSHTOS ; 2
184 0000FE NODUP: NEXT ; 4
185 000102
186 000102 ;C DROP x -- drop top of stack
187 000102 HEADER DROP,4,'DROP',DOCODE
188 00010C 3744 MOV @PSP+,TOS ; 2
189 00010E NEXT ; 4
190 000112
191 000112 ;C SWAP x1 x2 -- x2 x1 swap top two
items
192 000112 HEADER SWAP,4,'SWAP',DOCODE
193 00011C 2644 MOV @PSP,W ; 2
194 00011E 84470000 MOV TOS,0(PSP) ; 4
195 000122 0746 MOV W,TOS ; 1
196 000124 NEXT ; 4
197 000128
198 000128 ;C OVER x1 x2 -- x1 x2 x1 per stack
diagram
199 000128 HEADER OVER,4,'OVER',DOCODE
200 000132 2644 MOV @PSP,W ; 2
201 000134 2483 SUB #2,PSP ; 2
202 000136 84470000 MOV TOS,0(PSP) ; 4
203 00013A 0746 MOV W,TOS ; 1
204 00013C NEXT ; 4
205 000140
206 000140 ;C ROT x1 x2 x3 -- x2 x3 x1 per stack
diagram
207 000140 HEADER ROT,3,'ROT',DOCODE
208 00014A 2644 MOV @PSP,W ; 2 fetch
x2
209 00014C 84470000 MOV TOS,0(PSP) ; 4 store
x3
210 000150 17440200 MOV 2(PSP),TOS ; 3 fetch
x1
211 000154 84460200 MOV W,2(PSP) ; 4 store
x2
212 000158 NEXT ; 4
213 00015C
214 00015C ;X NIP x1 x2 -- x2 per stack
diagram
215 00015C HEADER NIP,3,'NIP',DOCODE
216 000166 2453 ADD #2,PSP ; 1
217 000168 NEXT ; 4
218 00016C
219 00016C ;C >R x -- R: -- x push to return
stack
220 00016C HEADER TOR,2,'>R',DOCODE
221 000174 0712 PUSH TOS
222 000176 3744 MOV @PSP+,TOS
223 000178 NEXT
224 00017C
225 00017C ;C R> -- x R: x -- pop from return
stack
226 00017C HEADER RFROM,2,'R>',DOCODE
227 000184 2483 SUB #2,PSP ; 2
228 000186 84470000 MOV TOS,0(PSP) ; 4
229 00018A 3741 MOV @RSP+,TOS
230 00018C NEXT
231 000190
232 000190 ;C R@ -- x R: x -- x fetch from rtn
stk
233 000190 HEADER RFETCH,2,'R@',DOCODE
234 000198 2483 SUB #2,PSP
235 00019A 84470000 MOV TOS,0(PSP)
236 00019E 2741 MOV @RSP,TOS
237 0001A0 NEXT
238 0001A4
239 0001A4 ;Z SP@ -- a-addr get data stack
pointer
240 0001A4 HEADER SPFETCH,3,'SP@',DOCODE
241 0001AE 2483 SUB #2,PSP
242 0001B0 84470000 MOV TOS,0(PSP)
243 0001B4 0744 MOV PSP,TOS
244 0001B6 NEXT
245 0001BA
246 0001BA ;Z SP! a-addr -- set data stack
pointer
247 0001BA HEADER SPSTORE,3,'SP!',DOCODE
248 0001C4 0447 MOV TOS,PSP
249 0001C6 3744 MOV @PSP+,TOS ; 2
250 0001C8 NEXT
251 0001CC
252 0001CC ;Z RP@ -- a-addr get return stack
pointer
253 0001CC HEADER RPFETCH,3,'RP@',DOCODE
254 0001D6 2483 SUB #2,PSP
255 0001D8 84470000 MOV TOS,0(PSP)
256 0001DC 0741 MOV RSP,TOS
257 0001DE NEXT
258 0001E2
259 0001E2 ;Z RP! a-addr -- set return stack
pointer
260 0001E2 HEADER RPSTORE,3,'RP!',DOCODE
261 0001EC 0147 MOV TOS,RSP
262 0001EE 3744 MOV @PSP+,TOS ; 2
263 0001F0 NEXT
264 0001F4
265 0001F4 ;X TUCK x1 x2 -- x2 x1 x2 per stack
diagram
266 0001F4 HEADER TUCK,4,'TUCK',DOCOLON
267 0001FE ............ DC16 SWAP,OVER,EXIT
268 000204
269 000204 ; ----------------------------------------------
------------------------
270 000204 ; MEMORY OPERATIONS
271 000204
272 000204 ;C @ a-addr -- x fetch cell from
memory
273 000204 HEADER FETCH,1,'@',DOCODE
274 00020C 2747 MOV @TOS,TOS
275 00020E NEXT
276 000212
277 000212 ;C ! x a-addr -- store cell in
memory
278 000212 HEADER STORE,1,'!',DOCODE
279 00021A B7440000 MOV @PSP+,0(TOS)
280 00021E 3744 MOV @PSP+,TOS
281 000220 NEXT
282 000224
283 000224 ;C C@ c-addr -- char fetch char from
memory
284 000224 HEADER CFETCH,2,'C@',DOCODE
285 00022C 6747 MOV.B @TOS,TOS
286 00022E NEXT
287 000232
288 000232 ;C C! char c-addr -- store char in
memory
289 000232 HEADER CSTORE,2,'C!',DOCODE
290 00023A 3644 MOV @PSP+,W
291 00023C C7460000 MOV.B W,0(TOS)
292 000240 3744 MOV @PSP+,TOS
293 000242 NEXT
294 000246
295 000246 ; FLASH MEMORY OPERATIONS
296 000246 ; Note that an I! or IC! to a RAM address
>FLASHSTART will work -- it
297 000246 ; will enable the flash, write the RAM, and then
disable the flash.
298 000246 ; An FLERASE to a RAM address will merely clear
that one RAM cell.
299 000246
300 000246 ;Z FLERASE a-addr n --
301 000246 HEADER FLERASE,7,'FLERASE',DOCODE
302 000254 3644 MOV @PSP+,W ; get address in
W
303 000256 0756 ADD W,TOS ; TOS=end adrs
(first unerased
adrs)
304 000258 FLE_1:
305 000258 0697 CMP TOS,W ; adr-end
306 00025A 282C JC FLE_X ; if no borrow,
adr>=end, do
not erase
307 00025C ; is it within Main flash?
308 00025C 369000C0 CMP #FLASHSTART,W ; flash
start
309 000260 0328 JNC FLE_INFO ; if borrow,
adrend, check
if Info
312 000268 FLE_INFO: ; is it within Info flash?
313 000268 36900010 CMP #INFOSTART,W
314 00026C 1F28 JNC FLE_X ; if borrow,
adrend, do not
erase
317 000274 FLE_OK: ; Address is either in Main flash, or in
Info flash.
318 000274 ; Segment Erase from flash.
319 000274 ; Assumes ACCVIE = NMIIE = OFIE = 0,
watchdog disabled.
320 000274 ; Per section 5.3.2 of MSP430 Family
User's Guide
321 000274 0212 PUSH SR ; Save global
interrupt
flag
322 000276 32C2 DINT ; Disable
interrupts
323 000278 B24000A52C01 MOV #FWKEY,&FCTL3 ; Clear
LOCK
324 00027E B24002A52801 MOV #FWKEY+ERASE,&FCTL1 ; Enable segment
erase
325 000284 B6430000 MOV #-1,0(W) ; Dummy write in
segment to
erase
326 000288 B24000A52801 MOV #FWKEY,&FCTL1 ; Done. Clear
erase
command.
327 00028E B24010A52C01 MOV #FWKEY+LOCK,&FCTL3 ; Done, set
LOCK
328 000294 3241 POP SR ; restore global
interrupt
flag
329 000296 ; Advance flash pointer by 512 bytes or
128 bytes
330 000296 ; is it within Main flash?
331 000296 369000C0 CMP #FLASHSTART,W
332 00029A 0528 JNC FL_INFO ; if borrow,
adrend, must
be Info
335 0002A2 36508001 ADD #(MAINSEG-INFOSEG),W
336 0002A6 36508000 FL_INFO: ADD #INFOSEG,W
337 0002AA D63F JMP FLE_1 ; continue till
past end or
outside
limits
338 0002AC 3744 FLE_X: MOV @PSP+,TOS
339 0002AE NEXT
340 0002B2
341 0002B2 ; Program Space (Flash) operators
342 0002B2
343 0002B2 ;Z I! x a-addr -- store cell in
Instruction memory
344 0002B2 HEADER ISTORE,2,'I!',DOCODE
345 0002BA 3644 MOV @PSP+,W ; get data to
write
346 0002BC 17B3 BIT #1,TOS
347 0002BE 1F20 JNZ IST_X ; if not even
address, do not
write
348 0002C0 2697 CMP @TOS,W
349 0002C2 1D24 JZ IST_X ; if memory is
desired value,
do not
write
350 0002C4 0212 PUSH SR ; Save global
interrupt flag
351 0002C6 ; is it within Main flash?
352 0002C6 379000C0 CMP #FLASHSTART,TOS
353 0002CA 0328 JNC IST_INFO ; if borrow,
adrend, check
if Info
356 0002D2 IST_INFO: ; is it within Info flash?
357 0002D2 37900010 CMP #INFOSTART,TOS
358 0002D6 0A28 JNC IST_RAM ; if borrow,
adrend, assume
it's RAM
361 0002DE IST_OK: ; Address is either in Main flash, or in
Info flash.
362 0002DE ; Byte/word write from flash.
363 0002DE ; Assumes location to write is already
erased
364 0002DE ; Assumes ACCVIE = NMIIE = OFIE = 0,
watchdog disabled.
365 0002DE ; Per section 5.3.3 of MSP430 Family
User's Guide
366 0002DE 32C2 DINT ; Disable
interrupts
367 0002E0 B24000A52C01 MOV #FWKEY,&FCTL3 ; Clear
LOCK
368 0002E6 B24040A52801 MOV #FWKEY+WRT,&FCTL1 ; Enable
write
369 0002EC IST_RAM: ; If RAM, jump here to write.
FCTL1,FCTL3,EINT are superfluous
370 0002EC 87460000 MOV W,0(TOS) ; Write word to
flash
location
371 0002F0 B24000A52801 MOV #FWKEY,&FCTL1 ; Done. Clear
WRT.
372 0002F6 B24010A52C01 MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK
373 0002FC 3241 POP SR ; restore global
interrupt
flag
374 0002FE 3744 IST_X: MOV @PSP+,TOS ; pop new
TOS
375 000300 NEXT
376 000304
377 000304 ;Z IC! x a-addr -- store char in
Instruction memory
378 000304 HEADER ICSTORE,3,'IC!',DOCODE
379 00030E 3644 MOV @PSP+,W ; get data to
write
380 000310 6697 CMP.B @TOS,W
381 000312 F527 JZ IST_X ; if memory is
desired value,
do not
write
382 000314 0212 PUSH SR ; Save global
interrupt
flag
383 000316 ; is it within Main flash?
384 000316 379000C0 CMP #FLASHSTART,TOS
385 00031A 0328 JNC ICST_INFO ; if borrow,
adrend, check
if Info
388 000322 ICST_INFO: ; is it within Info flash?
389 000322 37900010 CMP #INFOSTART,TOS
390 000326 0A28 JNC ICST_RAM ; if borrow,
adrend, assume
it's RAM
393 00032E ICST_OK: ; Address is either in Main flash, or
in Info flash.
394 00032E ; Byte/word write from flash.
395 00032E ; Assumes location to write is already
erased
396 00032E ; Assumes ACCVIE = NMIIE = OFIE = 0,
watchdog disabled.
397 00032E ; Per section 5.3.3 of MSP430 Family
User's Guide
398 00032E 32C2 DINT ; Disable
interrupts
399 000330 B24000A52C01 MOV #FWKEY,&FCTL3 ; Clear
LOCK
400 000336 B24040A52801 MOV #FWKEY+WRT,&FCTL1 ; Enable
write
401 00033C ICST_RAM: ; If RAM, jump here to write.
FCTL1,FCTL3,EINT are superfluous
402 00033C C7460000 MOV.B W,0(TOS) ; Write byte to
flash
location
403 000340 B24000A52801 MOV #FWKEY,&FCTL1 ; Done. Clear
WRT.
404 000346 B24010A52C01 MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK
405 00034C 3241 POP SR ; restore global
interrupt
flag
406 00034E D73F JMP IST_X
407 000350
408 000350 ;Z I@ a-addr -- x fetch cell from
Instruction memory
409 000350 HEADER IFETCH,2,'I@',FETCH+2
410 000358
411 000358 ;Z IC@ a-addr -- x fetch char from
Instruction memory
412 000358 HEADER ICFETCH,3,'IC@',CFETCH+2
413 000362
414 000362 ;Z D->I c-addr1 c-addr2 u -- move
Data->Code
415 000362 ; Block move from Data space to Code space.
Flashable.
416 000362 ; For the MSP430, this uses a "smart" algorithm
that uses word writes,
417 000362 ; rather than byte writes, whenever possible.
Note that byte reads
418 000362 ; are used for the source, so it need not be
aligned.
419 000362 HEADER DTOI,4,'D->I',DOCODE
420 00036C 3644 MOV @PSP+,W ; dest adrs
421 00036E 3A44 MOV @PSP+,X ; src adrs
422 000370 0793 CMP #0,TOS
423 000372 2124 JZ DTOI_X
424 000374 DTOI_LOOP: ; Begin flash write sequence
425 000374 0212 PUSH SR ; Save global
interrupt
flag
426 000376 32C2 DINT ; Disable
interrupts
427 000378 B24000A52C01 MOV #FWKEY,&FCTL3 ; Clear
LOCK
428 00037E B24040A52801 MOV #FWKEY+WRT,&FCTL1 ; Enable
write
429 000384 ; If length is 1, or dest. address is
odd, do a byte write.
430 000384 ; Else, do a word write.
431 000384 1793 CMP #1,TOS
432 000386 0B24 JZ DTOI_BYTE
433 000388 16B3 BIT #1,W
434 00038A 0920 JNZ DTOI_BYTE
435 00038C 7B4A DTOI_WORD: MOV.B @X+,Y ; get low byte
of word
436 00038E 7C4A MOV.B @X+,Q ; get high byte
of word
437 000390 8C10 SWPB Q
438 000392 0BDC BIS Q,Y ; merge
bytes
439 000394 864B0000 MOV.W Y,0(W) ; write byte to
dest
440 000398 2653 ADD #2,W
441 00039A 1783 SUB #1,TOS ; another 1 will
be subtracted
below
442 00039C 033C JMP DTOI_END
443 00039E F64A0000 DTOI_BYTE: MOV.B @X+,0(W) ; copy byte from
src to
dest
444 0003A2 1653 ADD #1,W
445 0003A4 DTOI_END: ; End flash write sequence
446 0003A4 B24000A52801 MOV #FWKEY,&FCTL1 ; Done. Clear
WRT.
447 0003AA B24010A52C01 MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK
448 0003B0 3241 POP SR ; restore global
interrupt
flag
449 0003B2 1783 SUB #1,TOS
450 0003B4 DF23 JNZ DTOI_LOOP
451 0003B6 3744 DTOI_X: MOV @PSP+,TOS ; pop new
TOS
452 0003B8 NEXT
453 0003BC
454 0003BC ; ----------------------------------------------
------------------------
455 0003BC ; ARITHMETIC OPERATIONS
456 0003BC
457 0003BC ;C + n1/u1 n2/u2 -- n3/u3 add
n1+n2
458 0003BC HEADER PLUS,1,'+',DOCODE
459 0003C4 3754 ADD @PSP+,TOS
460 0003C6 NEXT
461 0003CA
462 0003CA ;C +! n/u a-addr -- add cell to
memory
463 0003CA HEADER PLUSSTORE,2,'+!',DOCODE
464 0003D2 B7540000 ADD @PSP+,0(TOS)
465 0003D6 3744 MOV @PSP+,TOS
466 0003D8 NEXT
467 0003DC
468 0003DC ;X M+ d n -- d add single to
double
469 0003DC HEADER MPLUS,2,'M+',DOCODE
470 0003E4 84570200 ADD TOS,2(PSP)
471 0003E8 84630000 ADDC #0,0(PSP)
472 0003EC 3744 MOV @PSP+,TOS
473 0003EE NEXT
474 0003F2
475 0003F2 ;C - n1/u1 n2/u2 -- n3/u3 subtract
n1-n2
476 0003F2 HEADER MINUS,1,'-',DOCODE
477 0003FA 3644 MOV @PSP+,W
478 0003FC 0687 SUB TOS,W
479 0003FE 0746 MOV W,TOS
480 000400 NEXT
481 000404
482 000404 ;C AND x1 x2 -- x3 logical
AND
483 000404 HEADER ANDD,3,'AND',DOCODE
484 00040E 37F4 AND @PSP+,TOS
485 000410 NEXT
486 000414
487 000414 ;C OR x1 x2 -- x3 logical
OR
488 000414 HEADER ORR,2,'OR',DOCODE
489 00041C 37D4 BIS @PSP+,TOS
490 00041E NEXT
491 000422
492 000422 ;C XOR x1 x2 -- x3 logical
XOR
493 000422 HEADER XORR,3,'XOR',DOCODE
494 00042C 37E4 XOR @PSP+,TOS
495 00042E NEXT
496 000432
497 000432 ;C INVERT x1 -- x2 bitwise
inversion
498 000432 HEADER INVERT,6,'INVERT',DOCODE
499 00043E 37E3 XOR #-1,TOS
500 000440 NEXT
501 000444
502 000444 ;C NEGATE x1 -- x2 two's complement
503 000444 HEADER NEGATE,6,'NEGATE',DOCODE
504 000450 37E3 XOR #-1,TOS
505 000452 1753 ADD #1,TOS
506 000454 NEXT
507 000458
508 000458 ;C 1+ n1/u1 -- n2/u2 add 1 to
TOS
509 000458 HEADER ONEPLUS,2,'1+',DOCODE
510 000460 1753 ADD #1,TOS
511 000462 NEXT
512 000466
513 000466 ;C 1- n1/u1 -- n2/u2 subtract 1 from
TOS
514 000466 HEADER ONEMINUS,2,'1-',DOCODE
515 00046E 1783 SUB #1,TOS
516 000470 NEXT
517 000474
518 000474 ;Z >< x1 -- x2 swap bytes (not
ANSI)
519 000474 HEADER SWAPBYTES,2,'><',DOCODE
520 00047C 8710 SWPB TOS
521 00047E NEXT
522 000482
523 000482 ;C 2* x1 -- x2 arithmetic left
shift
524 000482 HEADER TWOSTAR,2,'2*',DOCODE
525 00048A 0757 ADD TOS,TOS
526 00048C NEXT
527 000490
528 000490 ;C 2/ x1 -- x2 arithmetic right
shift
529 000490 HEADER TWOSLASH,2,'2/',DOCODE
530 000498 0711 RRA TOS
531 00049A NEXT
532 00049E
533 00049E ;C LSHIFT x1 u -- x2 logical L shift u
places
534 00049E HEADER LSHIFT,6,'LSHIFT',DOCODE
535 0004AA 3644 MOV @PSP+,W
536 0004AC 37F01F00 AND #1Fh,TOS ; no need to
shift more than
16
537 0004B0 0324 JZ LSH_X
538 0004B2 0656 LSH_1: ADD W,W
539 0004B4 1783 SUB #1,TOS
540 0004B6 FD23 JNZ LSH_1
541 0004B8 0746 LSH_X: MOV W,TOS
542 0004BA NEXT
543 0004BE
544 0004BE ;C RSHIFT x1 u -- x2 logical R shift u
places
545 0004BE HEADER RSHIFT,6,'RSHIFT',DOCODE
546 0004CA 3644 MOV @PSP+,W
547 0004CC 37F01F00 AND #1Fh,TOS ; no need to
shift more than
16
548 0004D0 0424 JZ RSH_X
549 0004D2 12C3 RSH_1: CLRC
550 0004D4 0610 RRC W
551 0004D6 1783 SUB #1,TOS
552 0004D8 FC23 JNZ RSH_1
553 0004DA 0746 RSH_X: MOV W,TOS
554 0004DC NEXT
555 0004E0
556 0004E0 ; ----------------------------------------------
------------------------
557 0004E0 ; COMPARISON OPERATIONS
558 0004E0
559 0004E0 ;C 0= n/u -- flag return true if
TOS=0
560 0004E0 HEADER ZEROEQUAL,2,'0=',DOCODE
561 0004E8 1783 SUB #1,TOS ; borrow (clear cy)
if TOS was
0
562 0004EA 0777 SUBC TOS,TOS ; TOS=-1 if borrow
was set
563 0004EC NEXT
564 0004F0
565 0004F0 ;C 0< n -- flag true if TOS negative
566 0004F0 HEADER ZEROLESS,2,'0<',DOCODE
567 0004F8 0757 ADD TOS,TOS ; set cy if TOS
negative
568 0004FA 0777 SUBC TOS,TOS ; TOS=-1 if carry
was clear
569 0004FC 37E3 XOR #-1,TOS ; TOS=-1 if carry
was set
570 0004FE NEXT
571 000502
572 000502 ;C = x1 x2 -- flag test x1=x2
573 000502 HEADER EQUAL,1,'=',DOCODE
574 00050A 3644 MOV @PSP+,W
575 00050C 0687 SUB TOS,W ; x1-x2 in W, flags
set
576 00050E 1124 JZ TOSTRUE
577 000510 0743 TOSFALSE: MOV #0,TOS
578 000512 NEXT
579 000516
580 000516 ;X <> x1 x2 -- flag test not eq (not
ANSI)
581 000516 HEADER NOTEQUAL,2,'<>',DOCOLON
582 00051E ............ DW EQUAL,ZEROEQUAL,EXIT
583 000524
584 000524 ;C < n1 n2 -- flag test n1 n1 n2 -- flag test n1>n2,
signed
593 000538 HEADER GREATER,1,'>',DOCOLON
594 000540 ............ DW SWAP,LESS,EXIT
595 000546
596 000546 ;C U< u1 u2 -- flag test u1 u1 u2 -- flag u1>u2 unsgd (not
ANSI)
604 000556 HEADER UGREATER,2,'U>',DOCOLON
605 00055E ............ DW SWAP,ULESS,EXIT
606 000564
607 000564 ; ----------------------------------------------
------------------------
608 000564 ; LOOP AND BRANCH OPERATIONS
609 000564 ; These use relative branch addresses: a branch
is ADD @IP,IP
610 000564
611 000564 ;Z branch -- branch
always
612 000564 HEADER bran,6,'branch',DOCODE
613 000570 2555 dobran: ADD @IP,IP ; 2
614 000572 NEXT ; 4
615 000576
616 000576 ;Z ?branch x -- branch if TOS
zero
617 000576 HEADER qbran,7,'?branch',DOCODE
618 000584 0753 ADD #0,TOS ; 1 test TOS value
619 000586 3744 MOV @PSP+,TOS ; 2 pop new TOS value
(doesn't change
flags)
620 000588 F327 JZ dobran ; 2 if TOS was zero, take
the branch
621 00058A 2553 ADD #2,IP ; 1 else skip the
branch destination
622 00058C NEXT ; 4
623 000590
624 000590 ;Z (do) n1|u1 n2|u2 -- R: -- sys1 sys2
625 000590 ;Z run-time code for
DO
626 000590 ; '83 and ANSI standard loops terminate when the
boundary of
627 000590 ; limit-1 and limit is crossed, in either
direction. This can
628 000590 ; be conveniently implemented by making the
limit 8000h, so that
629 000590 ; arithmetic overflow logic can detect crossing.
I learned this
630 000590 ; trick from Laxen & Perry F83.
631 000590 ; fudge factor = 8000h-limit, to be added to the
start value.
632 000590 HEADER xdo,4,'(do)',DOCODE
633 00059A 2182 SUB #4,RSP ; push old loop
values on
return
stack
634 00059C 81490200 MOV LIMIT,2(RSP)
635 0005A0 81480000 MOV INDEX,0(RSP)
636 0005A4 39400080 MOV #8000h,LIMIT ; compute
8000h-limit
"fudge
factor"
637 0005A8 3984 SUB @PSP+,LIMIT
638 0005AA 0847 MOV TOS,INDEX ; loop ctr =
index+fudge
639 0005AC 0859 ADD LIMIT,INDEX
640 0005AE 3744 MOV @PSP+,TOS ; pop new
TOS
641 0005B0 NEXT
642 0005B4
643 0005B4 ;Z (loop) R: sys1 sys2 -- | sys1 sys2
644 0005B4 ;Z run-time code for
LOOP
645 0005B4 ; Add 1 to the loop index. If loop terminates,
clean up the
646 0005B4 ; return stack and skip the branch. Else take
the inline branch.
647 0005B4 ; Note that LOOP terminates when index=8000h.
648 0005B4 HEADER xloop,6,'(loop)',DOCODE
649 0005C0 1853 ADD #1,INDEX
650 0005C2 32B00001 BIT #100h,SR ; is overflow bit
set?
651 0005C6 D427 JZ dobran ; no overflow =
loop
652 0005C8 2553 ADD #2,IP ; overflow = loop
done, skip branch
ofs
653 0005CA 3841 MOV @RSP+,INDEX ; restore old loop
values
654 0005CC 3941 MOV @RSP+,LIMIT
655 0005CE NEXT
656 0005D2
657 0005D2 ;Z (+loop) n -- R: sys1 sys2 -- | sys1
sys2
658 0005D2 ;Z run-time code for
+LOOP
659 0005D2 ; Add n to the loop index. If loop terminates,
clean up the
660 0005D2 ; return stack and skip the branch. Else take
the inline branch.
661 0005D2 HEADER xplusloop,7,'(+loop)',DOCODE
662 0005E0 0857 ADD TOS,INDEX
663 0005E2 3744 MOV @PSP+,TOS ; get new TOS,
doesn't change
flags
664 0005E4 32B00001 BIT #100h,SR ; is overflow bit
set?
665 0005E8 C327 JZ dobran ; no overflow =
loop
666 0005EA 2553 ADD #2,IP ; overflow = loop
done, skip branch
ofs
667 0005EC 3841 MOV @RSP+,INDEX ; restore old loop
values
668 0005EE 3941 MOV @RSP+,LIMIT
669 0005F0 NEXT
670 0005F4
671 0005F4 ;C I -- n R: sys1 sys2 -- sys1
sys2
672 0005F4 ;C get the innermost loop
index
673 0005F4 HEADER II,1,'I',DOCODE
674 0005FC 2483 SUB #2,PSP ; make room in
TOS
675 0005FE 84470000 MOV TOS,0(PSP)
676 000602 0748 MOV INDEX,TOS ; index =
loopctr -
fudge
677 000604 0789 SUB LIMIT,TOS
678 000606 NEXT
679 00060A
680 00060A ;C J -- n R: 4*sys -- 4*sys
681 00060A ;C get the second loop
index
682 00060A HEADER JJ,1,'J',DOCODE
683 000612 2483 SUB #2,PSP ; make room in
TOS
684 000614 84470000 MOV TOS,0(PSP)
685 000618 2741 MOV @RSP,TOS ; index =
loopctr -
fudge
686 00061A 17810200 SUB 2(RSP),TOS
687 00061E NEXT
688 000622
689 000622 ;C UNLOOP -- R: sys1 sys2 -- drop loop
parms
690 000622 HEADER UNLOOP,6,'UNLOOP',DOCODE
691 00062E 3841 MOV @RSP+,INDEX ; restore old
loop values
692 000630 3941 MOV @RSP+,LIMIT
693 000632 NEXT
694 000636
695 000636 ;C (next) -- R: u1|0 -- u2|
696 000636 ; HEADER xnext,6,'(next)',DOCODE
697 000636 HEADLESS xnext,DOCODE
698 000638 91830000 SUB #1,0(RSP)
699 00063C 992F JC dobran
700 00063E 2153 ADD #2,RSP
701 000640 2553 ADD #2,IP
702 000642 NEXT
703 000646 ; ----------------------------------------------
------------------------
704 000646 ; MULTIPLY AND DIVIDE
705 000646
706 000646 ;C UM* u1 u2 -- ud unsigned 16x16->32
mult.
707 000646 HEADER UMSTAR,3,'UM*',DOCODE
708 000650 ; IROP1 = TOS register
709 000650 2A44 MOV @PSP,IROP2L ; get u1, leave
room on
stack
710 000652 ;
711 000652 ; T.I. SIGNED MULTIPLY SUBROUTINE: IROP1 x
IROP2L -> IRACM|IRACL
712 000652 0C43 MPYU: CLR IRACL ; 0 -> LSBs RESULT
713 000654 0D43 CLR IRACM ; 0 -> MSBs RESULT
714 000656 ; UNSIGNED MULTIPLY AND ACCUMULATE SUBROUTINE:
715 000656 ; (IROP1 x IROP2L) + IRACM|IRACL -> IRACM|IRACL
716 000656 0B43 MACU: CLR IROP2M ; MSBs MULTIPLIER
717 000658 1643 MOV #1,IRBT ; BIT TEST REGISTER
718 00065A 07B6 L$002: BIT IRBT,IROP1 ; TEST ACTUAL BIT
719 00065C 0224 JZ L$01 ; IF 0: DO NOTHING
720 00065E 0C5A ADD IROP2L,IRACL ; IF 1: ADD MULTIPLIER
TO RESULT
721 000660 0D6B ADDC IROP2M,IRACM
722 000662 0A5A L$01: RLA IROP2L ; MULTIPLIER x 2
723 000664 0B6B RLC IROP2M
724 000666 ;
725 000666 0656 RLA IRBT ; NEXT BIT TO TEST
726 000668 F82B JNC L$002 ; IF BIT IN CARRY:
FINISHED
727 00066A ; END T.I. ROUTINE section 5.1.1 of MSP430
Family Application Reports
728 00066A 844C0000 MOV IRACL,0(PSP) ; low result on
stack
729 00066E 074D MOV IRACM,TOS ; high result in
TOS
730 000670 NEXT
731 000674
732 000674 ;C UM/MOD ud u1 -- u2 u3 unsigned 32/16->16
733 000674 HEADER UMSLASHMOD,6,'UM/MOD',DOCODE
734 000680 ; IROP1 = TOS register
735 000680 3B44 MOV @PSP+,IROP2M ; get ud
hi
736 000682 2A44 MOV @PSP,IROP2L ; get ud lo,
leave room on
stack
737 000684 ;
738 000684 ; T.I. UNSIGNED DIVISION SUBROUTINE 32-BIT BY
16-BIT
739 000684 ; IROP2M|IROP2L : IROP1 -> IRACL REMAINDER IN
IROP2M
740 000684 ; RETURN: CARRY = 0: OK CARRY = 1: QUOTIENT > 16
BITS
741 000684 0C43 DIVIDE: CLR IRACL ; CLEAR RESULT
742 000686 36401100 MOV #17,IRBT ; INITIALIZE LOOP
COUNTER
743 00068A 0B97 DIV1: CMP IROP1,IROP2M ;
744 00068C 0128 JLO DIV2
745 00068E 0B87 SUB IROP1,IROP2M
746 000690 0C6C DIV2: RLC IRACL
747 000692 092C JC DIV4 ; Error: result > 16
bits
748 000694 1683 DEC IRBT ; Decrement loop counter
749 000696 0624 JZ DIV3 ; Is 0: terminate w/o
error
750 000698 0A5A RLA IROP2L
751 00069A 0B6B RLC IROP2M
752 00069C F62B JNC DIV1
753 00069E 0B87 SUB IROP1,IROP2M
754 0006A0 12D3 SETC
755 0006A2 F63F JMP DIV2
756 0006A4 12C3 DIV3: CLRC ; No error, C = 0
757 0006A6 DIV4: ; Error indication in C
758 0006A6 ; END T.I. ROUTINE Section 5.1.5 of MSP430
Family Application Reports
759 0006A6 844B0000 MOV IROP2M,0(PSP) ; remainder on
stack
760 0006AA 074C MOV IRACL,TOS ; quotient in
TOS
761 0006AC NEXT
762 0006B0
763 0006B0 ; ----------------------------------------------
------------------------
764 0006B0 ; BLOCK AND STRING OPERATIONS
765 0006B0
766 0006B0 ;C FILL c-addr u char -- fill memory with
char
767 0006B0 HEADER FILL,4,'FILL',DOCODE
768 0006BA 3A44 MOV @PSP+,X ; count
769 0006BC 3644 MOV @PSP+,W ; address
770 0006BE 0A93 CMP #0,X
771 0006C0 0524 JZ FILL_X
772 0006C2 C6470000 FILL_1: MOV.B TOS,0(W) ; store char in
memory
773 0006C6 1653 ADD #1,W
774 0006C8 1A83 SUB #1,X
775 0006CA FB23 JNZ FILL_1
776 0006CC 3744 FILL_X: MOV @PSP+,TOS ; pop new TOS
777 0006CE NEXT
778 0006D2
779 0006D2 ;X CMOVE c-addr1 c-addr2 u -- move from
bottom
780 0006D2 ; as defined in the ANSI optional String word
set
781 0006D2 ; On byte machines, CMOVE and CMOVE> are
logical
782 0006D2 ; factors of MOVE. They are easy to implement
on
783 0006D2 ; CPUs which have a block-move instruction.
784 0006D2 HEADER CMOVE,5,'CMOVE',DOCODE
785 0006DE 3644 MOV @PSP+,W ; dest adrs
786 0006E0 3A44 MOV @PSP+,X ; src adrs
787 0006E2 0793 CMP #0,TOS
788 0006E4 0524 JZ CMOVE_X
789 0006E6 F64A0000 CMOVE_1: MOV.B @X+,0(W) ; copy byte
790 0006EA 1653 ADD #1,W
791 0006EC 1783 SUB #1,TOS
792 0006EE FB23 JNZ CMOVE_1
793 0006F0 3744 CMOVE_X: MOV @PSP+,TOS ; pop new TOS
794 0006F2 NEXT
795 0006F6
796 0006F6 ;X CMOVE> c-addr1 c-addr2 u -- move from
top
797 0006F6 ; as defined in the ANSI optional String word
set
798 0006F6 HEADER CMOVEUP,6,'CMOVE>',DOCODE
799 000702 3644 MOV @PSP+,W ; dest adrs
800 000704 3A44 MOV @PSP+,X ; src adrs
801 000706 0793 CMP #0,TOS
802 000708 0824 JZ CMOVU_X
803 00070A 0657 ADD TOS,W ; start at
end
804 00070C 0A57 ADD TOS,X
805 00070E 1A83 CMOVU_1: SUB #1,X
806 000710 1683 SUB #1,W
807 000712 E64A0000 MOV.B @X,0(W) ; copy byte
808 000716 1783 SUB #1,TOS
809 000718 FA23 JNZ CMOVU_1
810 00071A 3744 CMOVU_X: MOV @PSP+,TOS ; pop new TOS
811 00071C NEXT
812 000720
813 000720 ;Z I->D c-addr1 c-addr2 u -- move
Code->Data
814 000720 ; Block move from Code space to Data space.
815 000720 ; On the MSP430, this is the same as CMOVE.
816 000720 HEADER ITOD,4,'I->D',CMOVE+2
817 00072A
818 00072A ;Z SKIP c-addr u c -- c-addr' u'
819 00072A ;Z skip matching
chars
820 00072A ; Although SKIP, SCAN, and S= are perhaps not
the ideal factors
821 00072A ; of WORD and FIND, they closely follow the
string operations
822 00072A ; available on many CPUs, and so are easy to
implement and fast.
823 00072A HEADER SKIP,4,'SKIP',DOCODE
824 000734 3A44 MOV @PSP+,X ; get count
825 000736 2644 MOV @PSP,W ; get address, leave
space on stack
826 000738 0A93 CMP #0,X
827 00073A 0524 JZ SKIP_X
828 00073C 6796 SKIP_1: CMP.B @W,TOS ; does character
match?
829 00073E 0320 JNZ SKIP_X ; no, we are
done
830 000740 1653 ADD #1,W
831 000742 1A83 SUB #1,X
832 000744 FB23 JNZ SKIP_1
833 000746 84460000 SKIP_X: MOV W,0(PSP) ; store updated
address on
stack
834 00074A 074A MOV X,TOS ; updated count to
TOS
835 00074C NEXT
836 000750
837 000750 ;Z SCAN c-addr u c -- c-addr' u'
838 000750 ;Z find matching char
839 000750 HEADER SCAN,4,'SCAN',DOCODE
840 00075A 3A44 MOV @PSP+,X ; get count
841 00075C 2644 MOV @PSP,W ; get address, leave
space on stack
842 00075E 0A93 CMP #0,X
843 000760 0524 JZ SCAN_X
844 000762 6796 SCAN_1: CMP.B @W,TOS ; does character
match?
845 000764 0324 JZ SCAN_X ; yes, we are
done
846 000766 1653 ADD #1,W
847 000768 1A83 SUB #1,X
848 00076A FB23 JNZ SCAN_1
849 00076C 84460000 SCAN_X: MOV W,0(PSP) ; store updated
address on
stack
850 000770 074A MOV X,TOS ; updated count to
TOS
851 000772 NEXT
852 000776
853 000776 ;Z S= c-addr1 c-addr2 u -- n string
compare
854 000776 ;Z n<0: s10:
s1>s2
855 000776 HEADER SEQUAL,2,'S=',DOCODE
856 00077E 3644 MOV @PSP+,W ; adrs2
857 000780 3A44 MOV @PSP+,X ; adrs1
858 000782 0793 CMP #0,TOS
859 000784 0A24 JZ SEQU_X
860 000786 FA960000 SEQU_1: CMP.B @W+,0(X) ; compare char1-char
2
861 00078A 0420 JNZ SMISMATCH
862 00078C 1A53 ADD #1,X
863 00078E 1783 SUB #1,TOS
864 000790 FA23 JNZ SEQU_1
865 000792 ; no mismatch found, strings are equal,
TOS=0
866 000792 033C JMP SEQU_X
867 000794 ; mismatch found, CY clear if borrow set
(s10:
s1>s2
875 00079E ; For Harvard model, c-addr1 is Data, c-addr2 is
Header.
876 00079E ; On MSP430, both use the same fetch instruction
, so N= is the same as S=.
877 00079E HEADER NEQUAL,2,'N=',SEQUAL+2
878 0007A6
879 0007A6 ; ----------------------------------------------
------------------------
880 0007A6 ; TERMINAL I/O
881 0007A6
882 0007A6 ;C EMIT c -- output character to
console
883 0007A6 HEADER EMIT,4,'EMIT',DOCODE
884 0007B0 EMITLOOP:
885 0007B0 E2B30300 BIT.B #UCA0TXIFG,&IFG2
886 0007B4 FD27 JZ EMITLOOP
887 0007B6 C2476700 MOV.B TOS,&UCA0TXBUF
888 0007BA 3744 MOV @PSP+,TOS
889 0007BC NEXT
890 0007C0
891 0007C0 ;C KEY -- c get character from
keyboard
892 0007C0 HEADER KEY,3,'KEY',DOCODE
893 0007CA KEYLOOP:
894 0007CA D2B30300 BIT.B #UCA0RXIFG,&IFG2
895 0007CE FD27 JZ KEYLOOP
896 0007D0 2483 SUB #2,PSP ; 1 push old
TOS..
897 0007D2 84470000 MOV TOS,0(PSP) ; 4 ..onto
stack
898 0007D6 57426600 MOV.B &UCA0RXBUF,TOS ; read
character
into
TOS
899 0007DA donoop:
900 0007DA donext: NEXT
901 0007DE
902 0007DE ;X KEY? -- f return true if char
waiting
903 0007DE HEADER KEYQ,4,'KEY?',DOCODE
904 0007E8 2483 SUB #2,PSP ; 1 push old
TOS..
905 0007EA 84470000 MOV TOS,0(PSP) ; 4 ..onto
stack
906 0007EE D2B30300 BIT.B #UCA0RXIFG,&IFG2
907 0007F2 9F22 JNZ TOSTRUE
908 0007F4 8D3E JMP TOSFALSE
909 0007F6
910 0007F6 ; ----------------------------------------------
------------------------
911 0007F6 ; We #include the following source files, rather
than compiling them
912 0007F6 ; separately, so that they can inherit the value
of 'link'.
913 0007F6
914 0007F6 #include "deps430G2553.s43"
1 0007F6 ; ----------------------------------------------
------------------------
2 0007F6 ; CF430G2553 is a Forth based on CamelForth
3 0007F6 ; for the Texas Instruments MSP430
4 0007F6 ;
5 0007F6 ; This program is free software; you can
redistribute it and/or modify
6 0007F6 ; it under the terms of the GNU General Public
License as published by
7 0007F6 ; the Free Software Foundation; either version 3
of the License, or
8 0007F6 ; (at your option) any later version.
9 0007F6 ;
10 0007F6 ; This program is distributed in the hope that
it will be useful,
11 0007F6 ; but WITHOUT ANY WARRANTY; without even the
implied warranty of
12 0007F6 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the
13 0007F6 ; GNU General Public License for more details.
14 0007F6 ;
15 0007F6 ; You should have received a copy of the GNU
General Public License
16 0007F6 ; along with this program. If not, see
.
17 0007F6 ;
18 0007F6 ; See LICENSE TERMS in Brads file readme.txt as
well.
19 0007F6
20 0007F6 ; ----------------------------------------------
------------------------
21 0007F6 ; deps430.s43: CPU and Model Dependencies -
MSP430G2553
22 0007F6 ; ----------------------------------------------
------------------------
23 0007F6
24 0007F6 ; Forth words are documented as follows:
25 0007F6 ;x NAME stack -- stack description
26 0007F6 ; where x=C for ANS Forth Core words, X for
ANS
27 0007F6 ; Extensions, Z for internal or private words,
U for Utilities.
28 0007F6 ;
29 0007F6 ; Indirect-Threaded Forth model for T.I.
MSP430
30 0007F6 ; cell size is 16 bits (2 bytes)
31 0007F6 ; char size is 8 bits (1 byte)
32 0007F6 ; address unit is 8 bits (1 byte), i.e.,
addresses are byte-aligned.
33 0007F6 ; ----------------------------------------------
------------------------
34 0007F6
35 0007F6 ; ----------------------------------------------
------------------------
36 0007F6 ; ALIGNMENT AND PORTABILITY OPERATORS
37 0007F6 ; Many of these are synonyms for other
words,
38 0007F6 ; and so are defined as CODE words.
39 0007F6
40 0007F6 ;C ALIGN -- align
HERE
41 0007F6 ; IHERE 1 AND IALLOT ;
42 0007F6 HEADER ALIGNN,5,'ALIGN',DOCOLON
43 000802 ........0100* DW IHERE,lit,1,ANDD,IALLOT,EXIT
44 00080E
45 00080E ;C ALIGNED addr -- a-addr align given
addr
46 00080E ; DUP 1 AND + ;
47 00080E HEADER ALIGNED,7,'ALIGNED',DOCOLON
48 00081C ........0100* DW DUP,lit,1,ANDD,PLUS,EXIT
49 000828
50 000828 ;Z CELL -- n size of one
cell
51 000828 HEADER CELL,4,'CELL',DOCON
52 000832 0200 dw 2
53 000834
54 000834 ;C CELL+ a-addr1 -- a-addr2 add cell
size
55 000834 ; 2 + ;
56 000834 HEADER CELLPLUS,5,'CELL+',DOCODE
57 000840 2753 ADD #2,TOS
58 000842 CB3F JMP donext
59 000844
60 000844 ;C CELLS n1 -- n2 cells->adrs
units
61 000844 HEADER CELLS,5,'CELLS',TWOSTAR+2
62 000850
63 000850 ;C CHAR+ c-addr1 -- c-addr2 add char
size
64 000850 HEADER CHARPLUS,5,'CHAR+',ONEPLUS+2
65 00085C
66 00085C ;C CHARS n1 -- n2 chars->adrs
units
67 00085C HEADER CHARS,5,'CHARS',donoop
68 000868
69 000868 ;C >BODY xt -- a-addr adrs of CREATE
data
70 000868 ; 2+ ; 8086 (3 byte
CALL)
71 000868 HEADER TOBODY,5,'>BODY',CELLPLUS+2
72 000874
73 000874 ;X COMPILE, xt -- append execution
token
74 000874 ; I called this word ,XT before I discovered
that it is defined in the
75 000874 ; ANSI standard as COMPILE,. On a DTC Forth this
simply appends xt
76 000874 ; (like , ) but on an STC Forth this must append
'CALL xt'.
77 000874 HEADER COMMAXT,8,'COMPILE,',DOALIAS
78 000882 .... DW ICOMMA
79 000884
80 000884 ;Z !CF adrs cfa -- set code action of a
word
81 000884 ; I! ;
82 000884 ; Indirect threaded model just stores adrs in
cfa field.
83 000884 HEADER STORECF,3,'!CF',DOALIAS
84 00088E .... DW ISTORE
85 000890
86 000890 ;Z ,CF adrs -- append a code field
87 000890 ; IHERE !CF 2 IALLOT ; MSP430 VERSION (2
bytes)
88 000890 HEADER COMMACF,3,',CF',DOCOLON
89 00089A ............* DW IHERE,STORECF,lit,2,IALLOT,EXIT
90 0008A6
91 0008A6 ;Z ,CALL adrs -- append a subroutine
CALL
92 0008A6 ; MSP430: 128x is call, Ad=11, Dreg=0000 (PC)
thus append 12B0,adrs.
93 0008A6 HEADER COMMACALL,5,',CALL',DOCOLON
94 0008B2 ....B012....* DW lit,12B0h,ICOMMA,ICOMMA,EXIT
95 0008BC
96 0008BC ;Z ,JMP adrs -- append an absolute
16-bit JMP (MOV #xx,PC)
97 0008BC ; MSP430: opcode 4, Sreg=0000, Ad=0, As=11
(immed), Dreg=0000 (PC)
98 0008BC ; thus append 4030,adrs.
99 0008BC HEADER COMMAJMP,4,',JMP',DOCOLON
100 0008C6 ....3040....* DW lit,4030h,ICOMMA,ICOMMA,EXIT
101 0008D0
102 0008D0 ;Z !COLON -- change code field to
DOCOLON
103 0008D0 ; -2 IALLOT DOCOLON-adrs ,CF ;
104 0008D0 ; This should be used immediately after
CREATE.
105 0008D0 ; This is made a distinct word, because on an
STC
106 0008D0 ; Forth, colon definitions have no code
field.
107 0008D0 HEADER STORCOLON,6,'!COLON',DOCOLON
108 0008DC ....FEFF.... DW lit,-2,IALLOT
109 0008E2 ............* DW lit,DOCOLON,COMMACF,EXIT
110 0008EA
111 0008EA ;Z ,EXIT -- append hi-level EXIT
action
112 0008EA ; ['] EXIT ,XT ;
113 0008EA ; This is made a distinct word, because on an
STC
114 0008EA ; Forth, it appends a RET instruction, not an
xt.
115 0008EA HEADER CEXIT,5,',EXIT',DOCOLON
116 0008F6 ............* DW lit,EXIT,COMMAXT,EXIT
117 0008FE
118 0008FE ; ----------------------------------------------
------------------------
119 0008FE ; CONTROL STRUCTURES
120 0008FE ; These words allow Forth control structure
words
121 0008FE ; to be defined portably.
122 0008FE
123 0008FE ;Z ,BRANCH xt -- append a branch instructio
n
124 0008FE ; xt is the branch operator to use, e.g. qbranch
or (loop).
125 0008FE ; It does NOT append the destination address.
126 0008FE ; On the MSP430 this is equivalent to ,XT
(above).
127 0008FE HEADER COMMABRANCH,7,',BRANCH',DOALIAS
128 00090C .... DW ICOMMA
129 00090E
130 00090E ;Z ,DEST dest -- append a branch
address
131 00090E ; IHERE - , ;
132 00090E ; This appends the given destination address to
the branch instruction.
133 00090E ; The MSP430 uses relative addressing from the
location of the offset cell,
134 00090E ; i.e., to branch to FOO the offset cell at $
contains FOO-$.
135 00090E HEADER COMMADEST,5,',DEST',DOCOLON
136 00091A ............* DW IHERE,MINUS,ICOMMA,EXIT
137 000922
138 000922 ;Z !DEST dest adrs -- change a branch
dest'n
139 000922 ; TUCK - SWAP I! ;
140 000922 ; Changes the destination address found at
'adrs' to the given 'dest'.
141 000922 ; The MSP430 uses relative addressing from the
location of the offset cell,
142 000922 ; i.e., to branch to FOO the offset cell at $
contains FOO-$.
143 000922 HEADER STOREDEST,5,'!DEST',DOCOLON
144 00092E ............* DW TUCK,MINUS,SWAP,ISTORE,EXIT
145 000938
146 000938 ;Z ,NONE -- append a null
destination (Flashable)
147 000938 ; CELL IALLOT ;
148 000938 ; When compiling in Flash ROM a branch to be
resolved later, we must
149 000938 ; skip the cell so that it can be programmed at
a later time.
150 000938 ; In general Flash memory can only be written
once!
151 000938 ; ,NONE should be used wherever !DEST will
resolve the branch.
152 000938 HEADER COMMANONE,5,',NONE',DOCOLON
153 000944 ............ DW CELL,IALLOT,EXIT
154 00094A
155 00094A ; ----------------------------------------------
------------------------
156 00094A ; HEADER STRUCTURE
157 00094A ; The structure of the Forth dictionary headers
(name, link, immediate
158 00094A ; flag, and "smudge" bit) does not necessarily
differ across CPUs. This
159 00094A ; structure is not easily factored into distinct
"portable" words;
160 00094A ; instead, it is implicit in the definitions of
FIND and CREATE, and
161 00094A ; also in NFA>LFA, NFA>CFA, IMMED?, IMMEDIATE,
HIDE, and REVEAL.
162 00094A ; These words must be (substantially) rewritten
if either the header
163 00094A ; structure or its inherent assumptions are
changed.
164 00094A
915 00094A #include "hilvl430G2553.s43"
1 00094A ; ----------------------------------------------
------------------------
2 00094A ; CF430G2553 is a Forth based on CamelForth
3 00094A ; for the Texas Instruments MSP430
4 00094A ;
5 00094A ; This program is free software; you can
redistribute it and/or modify
6 00094A ; it under the terms of the GNU General Public
License as published by
7 00094A ; the Free Software Foundation; either version 3
of the License, or
8 00094A ; (at your option) any later version.
9 00094A ;
10 00094A ; This program is distributed in the hope that
it will be useful,
11 00094A ; but WITHOUT ANY WARRANTY; without even the
implied warranty of
12 00094A ; MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the
13 00094A ; GNU General Public License for more details.
14 00094A ;
15 00094A ; You should have received a copy of the GNU
General Public License
16 00094A ; along with this program. If not, see
.
17 00094A ;
18 00094A ; See LICENSE TERMS in Brads file readme.txt as
well.
19 00094A
20 00094A ; ----------------------------------------------
------------------------
21 00094A ; hilvl430G2553.s43 - High Level Words -
MSP430G2553
22 00094A ; ----------------------------------------------
------------------------
23 00094A
24 00094A ; Forth words are documented as follows:
25 00094A ;x NAME stack -- stack description
26 00094A ; where x=C for ANS Forth Core words, X for
ANS
27 00094A ; Extensions, Z for internal or private
words.
28 00094A ; ----------------------------------------------
------------------------
29 00094A ; REVISION HISTORY
30 00094A
31 00094A ; 30 Mar 2012 mk fixed FM/MOD
32 00094A ; 26 Feb 2012 mk - adopted to MSP430G2553
33 00094A ; kernel at $E000, IDP = FLASHSTART =
$C000
34 00094A ; fixed backspace.
35 00094A ; ok promt at end of line.
36 00094A ; .S prints depth.
37 00094A ;
38 00094A ; 17 jan 09 bjr - changed label _DP to DDP for
compatibility with token
39 00094A ; naming convention. Now uses DEST macro to
compute branch offsets.
40 00094A ; 11 jan 09 bjr - modified QUIT for Xon/Xoff
flow control
41 00094A ; 4 jan 09 bjr - created from Camel86h.asm.
42 00094A
43 00094A ; SYSTEM VARIABLES & CONSTANTS =================
=
44 00094A
45 00094A ;Z u0 -- a-addr current user area
adrs
46 00094A ; 0 USER U0
47 00094A HEADER U0,2,'U0',DOUSER
48 000952 0000 DW 0
49 000954
50 000954 ;C >IN -- a-addr holds offset into
TIB
51 000954 ; 2 USER >IN
52 000954 HEADER TOIN,3,'>IN',DOUSER
53 00095E 0200 DW 2
54 000960
55 000960 ;C BASE -- a-addr holds conversion
radix
56 000960 ; 4 USER BASE
57 000960 HEADER BASE,4,'BASE',DOUSER
58 00096A 0400 DW 4
59 00096C
60 00096C ;C STATE -- a-addr holds compiler
state
61 00096C ; 6 USER STATE
62 00096C HEADER STATE,5,'STATE',DOUSER
63 000978 0600 DW 6
64 00097A
65 00097A ;Z dp -- a-addr holds dictionary
ptr
66 00097A ; 8 USER DP
67 00097A HEADER DDP,2,'DP',DOUSER
68 000982 0800 DW 8
69 000984
70 000984 ;Z 'source -- a-addr two cells: len,
adrs
71 000984 ; 10 USER 'SOURCE
72 000984 HEADER TICKSOURCE,7,'\'SOURCE',DOUSER
73 000992 0A00 DW 10
74 000994
75 000994 ;Z latest -- a-addr last word in
dict.
76 000994 ; 14 USER LATEST
77 000994 HEADER LATEST,6,'LATEST',DOUSER
78 0009A0 0E00 DW 14
79 0009A2
80 0009A2 ;Z hp -- a-addr HOLD pointer
81 0009A2 ; 16 USER HP
82 0009A2 HEADER HP,2,'HP',DOUSER
83 0009AA 1000 DW 16
84 0009AC
85 0009AC ;Z LP -- a-addr Leave-stack pointer
86 0009AC ; 18 USER LP
87 0009AC HEADER LP,2,'LP',DOUSER
88 0009B4 1200 DW 18
89 0009B6
90 0009B6 ;Z IDP -- a-addr ROM dictionary
pointer
91 0009B6 ; 20 USER IDP
92 0009B6 HEADER IDP,3,'IDP',DOUSER
93 0009C0 1400 DW 20
94 0009C2
95 0009C2 ;Z NEWEST -- a-addr temporary LATEST
storage
96 0009C2 ; 22 USER NEWEST
97 0009C2 HEADER NEWEST,6,'NEWEST',DOUSER
98 0009CE 1600 DW 22
99 0009D0
100 0009D0 ;Z APP -- a-addr xt of app ( was
TURNKEY)
101 0009D0 ; 24 USER APP
102 0009D0 HEADER APP,3,'APP',DOUSER
103 0009DA 1800 DW 24
104 0009DC
105 0009DC ;Z CAPS -- a-addr capitalize
words
106 0009DC ; 26 USER CAPS
107 0009DC HEADER CAPS,4,'CAPS',DOUSER
108 0009E6 1A00 DW 26
109 0009E8
110 0009E8 ; user variables 28,30 tbd
111 0009E8
112 0009E8 ;X PAD -- a-addr user PAD buffer
113 0009E8 ; = end of hold
area!
114 0009E8 HEADER PAD,3,'PAD',DOUSER
115 0009F2 .... DW PADAREA-UAREA
116 0009F4
117 0009F4 ;Z l0 -- a-addr bottom of Leave
stack
118 0009F4 HEADER L0,2,'L0',DOUSER
119 0009FC .... DW LSTACK-UAREA
120 0009FE
121 0009FE ;Z r0 -- a-addr end of return
stack
122 0009FE HEADER RZERO,2,'R0',DOUSER
123 000A06 .... DW RSTACK-UAREA
124 000A08
125 000A08 ;Z s0 -- a-addr end of parameter
stack
126 000A08 HEADER S0,2,'S0',DOUSER
127 000A10 .... DW PSTACK-UAREA
128 000A12
129 000A12 ;X tib -- a-addr Terminal Input
Buffer
130 000A12 ; HEX 80 USER TIB 8086: above user
area
131 000A12 HEADER TIB,3,'TIB',DOUSER
132 000A1C .... DW TIBAREA-UAREA
133 000A1E
134 000A1E ;Z tibsize -- n size of TIB
135 000A1E HEADER TIBSIZE,7,'TIBSIZE',DOCON
136 000A2C .... DW TIB_SIZE-2 ; 2 chars safety zone
137 000A2E
138 000A2E ;C BL -- char an ASCII
space
139 000A2E HEADER BLANK,2,'BL',DOCON
140 000A36 2000 DW 20h
141 000A38
142 000A38 ;Z uinit -- addr initial values for user
area
143 000A38 ; MSP430: we also use this to initialize the RAM
interrupt
144 000A38 ; vectors, which immediately follow the user
area.
145 000A38 ; Per init430f1611.s43, allocate 16 cells for
user
146 000A38 ; variables, followed by 30 cells for interrupt
vectors.
147 000A38 HEADER UINIT,5,'UINIT',DOROM
148 000A44 000000000A00* DW 0,0,10,0 ; reserved,>IN,BASE,STAT
E ; start in HEX
mk
149 000A4C .... DW RAMDICT ; DP
150 000A4E 00000000 DW 0,0 ; SOURCE init'd
elsewhere
151 000A52 .... DW lastword ; LATEST
152 000A54 00000000 DW 0,0 ; HP,LP init'd
elsewhere
153 000A58 00C0 DW FLASHSTART ; IDP
154 000A5A 0000 DW 0 ; NEWEST not init'd
155 000A5C .... DW DOTCOLD ; app
156 000A5E FFFF DW -1 ; CAPS on
157 000A60 00000000 DW 0,0 ; user variables
TBD
158 000A64
159 000A64 /* not there mk
160 000A64 ; RAM interrupt vectors, 15 vectors of 2 cells
each
161 000A64 MOV #nullirq,PC
162 000A64 MOV #nullirq,PC
163 000A64 MOV #nullirq,PC
164 000A64 MOV #nullirq,PC
165 000A64 MOV #nullirq,PC
166 000A64 MOV #nullirq,PC
167 000A64 MOV #nullirq,PC
168 000A64 MOV #nullirq,PC
169 000A64 MOV #nullirq,PC
170 000A64 MOV #nullirq,PC
171 000A64 MOV #nullirq,PC
172 000A64 MOV #nullirq,PC
173 000A64 MOV #nullirq,PC
174 000A64 MOV #nullirq,PC
175 000A64 MOV #nullirq,PC
176 000A64 */
177 000A64
178 000A64 ;Z #init -- n #bytes of user area init
data
179 000A64 HEADER NINIT,5,'#INIT',DOCON
180 000A70 .... DW (UAREA_SIZE)*2 ; SIZEs given in
cells
181 000A72
182 000A72
183 000000 EXTERN cor,infoB,AppU0
184 000A72 ;Z COR -- adr cause of reset
185 000A72 HEADER COR,3,'COR',DOCON
186 000A7C .... DW cor
187 000A7E
188 000A7E ;Z INFOB -- adr start of info B
segment
189 000A7E HEADER INFOB,5,'INFOB',DOCON
190 000A8A .... DW infoB
191 000A8C
192 000A8C ;Z APPU0 -- adr start of Application
user area
193 000A8C HEADER APPU0,5,'APPU0',DOCON
194 000A98 .... DW AppU0
195 000A9A
196 000A9A
197 000A9A ; ARITHMETIC OPERATORS =========================
=
198 000A9A
199 000A9A ;C S>D n -- d single -> double
prec.
200 000A9A ; DUP 0< ;
201 000A9A HEADER STOD,3,'S>D',DOCOLON
202 000AA4 ............ DW DUP,ZEROLESS,EXIT
203 000AAA
204 000AAA ;Z ?NEGATE n1 n2 -- n3 negate n1 if n2
negative
205 000AAA ; 0< IF NEGATE THEN ; ...a common
factor
206 000AAA HEADER QNEGATE,7,'?NEGATE',DOCOLON
207 000AB8 ........ DW ZEROLESS,qbran
208 000ABC DEST QNEG1
209 000ABE .... DW NEGATE
210 000AC0 .... QNEG1: DW EXIT
211 000AC2
212 000AC2 ;C ABS n1 -- +n2 absolute value
213 000AC2 ; DUP ?NEGATE ;
214 000AC2 HEADER ABBS,3,'ABS',DOCOLON
215 000ACC ............ DW DUP,QNEGATE,EXIT
216 000AD2
217 000AD2 ;X DNEGATE d1 -- d2 negate double
precision
218 000AD2 ; SWAP INVERT SWAP INVERT 1 M+ ;
219 000AD2 HEADER DNEGATE,7,'DNEGATE',DOCOLON
220 000AE0 ............* DW SWAP,INVERT,SWAP,INVERT,lit,1,MPLUS
221 000AEE .... DW EXIT
222 000AF0
223 000AF0 ;Z ?DNEGATE d1 n -- d2 negate d1 if n
negative
224 000AF0 ; 0< IF DNEGATE THEN ; ...a common
factor
225 000AF0 HEADER QDNEGATE,8,'?DNEGATE',DOCOLON
226 000AFE ........ DW ZEROLESS,qbran
227 000B02 DEST DNEG1
228 000B04 .... DW DNEGATE
229 000B06 .... DNEG1: DW EXIT
230 000B08
231 000B08 ;X DABS d1 -- +d2 absolute value
dbl.prec.
232 000B08 ; DUP ?DNEGATE ;
233 000B08 HEADER DABS,4,'DABS',DOCOLON
234 000B12 ............ DW DUP,QDNEGATE,EXIT
235 000B18
236 000B18 ;C M* n1 n2 -- d signed 16*16->32
multiply
237 000B18 ; 2DUP XOR >R carries sign of the
result
238 000B18 ; SWAP ABS SWAP ABS UM*
239 000B18 ; R> ?DNEGATE ;
240 000B18 HEADER MSTAR,2,'M*',DOCOLON
241 000B20 ............ DW TWODUP,XORR,TOR
242 000B26 ............* DW SWAP,ABBS,SWAP,ABBS,UMSTAR
243 000B30 ............ DW RFROM,QDNEGATE,EXIT
244 000B36
245 000B36 ;C SM/REM d1 n1 -- n2 n3 symmetric signed
div
246 000B36 ; 2DUP XOR >R sign of quotient
247 000B36 ; OVER >R sign of remainder
248 000B36 ; ABS >R DABS R> UM/MOD
249 000B36 ; SWAP R> ?NEGATE
250 000B36 ; SWAP R> ?NEGATE ;
251 000B36 ; Ref. dpANS-6 section 3.2.2.1.
252 000B36 HEADER SMSLASHREM,6,'SM/REM',DOCOLON
253 000B42 ............* DW TWODUP,XORR,TOR,OVER,TOR
254 000B4C ............* DW ABBS,TOR,DABS,RFROM,UMSLASHMOD
255 000B56 ............* DW SWAP,RFROM,QNEGATE,SWAP,RFROM,QNEGATE
256 000B62 .... DW EXIT
257 000B64
258 000B64 ;C FM/MOD d1 n1 -- n2 n3 floored signed
div'n
259 000B64 ; Ching-Tang Tseng
Mar 24 2012
260 000B64 ; DUP >R OVER OVER XOR >R
261 000B64 ; SM/REM
262 000B64 ; OVER R> 0< AND
263 000B64 ; IF SWAP R@ + SWAP 1 -
264 000B64 ; THEN R> DROP ;
265 000B64 ; 1 0 2 FM/MOD(OK) . . 0 1 ok
266 000B64 ; 7 0 9 FM/MOD(OK) . . 0 7 ok
267 000B64 ; Ref. dpANS-6 section 3.2.2.1.
268 000B64 HEADER FMSLASHMOD,6,'FM/MOD',DOCOLON
269 000B70 ............* DW DUP,TOR,OVER,OVER,XORR,TOR
270 000B7C .... DW SMSLASHREM
271 000B7E ............* DW OVER,RFROM,ZEROLESS,ANDD,qbran
272 000B88 DEST FMMOD1
273 000B8A ............* DW SWAP,RFETCH,PLUS,SWAP,ONEMINUS
274 000B94 ............ FMMOD1: DW RFROM,DROP,EXIT
275 000B9A
276 000B9A ;C * n1 n2 -- n3 signed multiply
277 000B9A ; M* DROP ;
278 000B9A HEADER STAR,1,'*',DOCOLON
279 000BA2 ............ DW MSTAR,DROP,EXIT
280 000BA8
281 000BA8 ;C /MOD n1 n2 -- n3 n4 signed divide/rem'dr
282 000BA8 ; >R S>D R> FM/MOD ;
283 000BA8 HEADER SLASHMOD,4,'/MOD',DOCOLON
284 000BB2 ............* DW TOR,STOD,RFROM,FMSLASHMOD,EXIT
285 000BBC
286 000BBC ;C / n1 n2 -- n3 signed divide
287 000BBC ; /MOD nip ;
288 000BBC HEADER SLASH,1,'/',DOCOLON
289 000BC4 ............ DW SLASHMOD,NIP,EXIT
290 000BCA
291 000BCA ;C MOD n1 n2 -- n3 signed remainder
292 000BCA ; /MOD DROP ;
293 000BCA HEADER MODD,3,'MOD',DOCOLON
294 000BD4 ............ DW SLASHMOD,DROP,EXIT
295 000BDA
296 000BDA ;C */MOD n1 n2 n3 -- n4 n5 n1*n2/n3,
rem"
297 000BDA ; >R M* R> FM/MOD ;
298 000BDA HEADER SSMOD,5,'*/MOD',DOCOLON
299 000BE6 ............* DW TOR,MSTAR,RFROM,FMSLASHMOD,EXIT
300 000BF0
301 000BF0 ;C */ n1 n2 n3 -- n4 n1*n2/n3
302 000BF0 ; */MOD nip ;
303 000BF0 HEADER STARSLASH,2,'*/',DOCOLON
304 000BF8 ............ DW SSMOD,NIP,EXIT
305 000BFE
306 000BFE ;C MAX n1 n2 -- n3 signed maximum
307 000BFE ; 2DUP < IF SWAP THEN DROP ;
308 000BFE HEADER MAX,3,'MAX',DOCOLON
309 000C08 ............ DW TWODUP,LESS,qbran
310 000C0E DEST MAX1
311 000C10 .... DW SWAP
312 000C12 ........ MAX1: DW DROP,EXIT
313 000C16
314 000C16 ;C MIN n1 n2 -- n3 signed minimum
315 000C16 ; 2DUP > IF SWAP THEN DROP ;
316 000C16 HEADER MIN,3,'MIN',DOCOLON
317 000C20 ............ DW TWODUP,GREATER,qbran
318 000C26 DEST MIN1
319 000C28 .... DW SWAP
320 000C2A ........ MIN1: DW DROP,EXIT
321 000C2E
322 000C2E ; DOUBLE OPERATORS =============================
=
323 000C2E
324 000C2E ;C 2@ a-addr -- x1 x2 fetch 2 cells
325 000C2E ; DUP CELL+ @ SWAP @ ;
326 000C2E ; the lower address will appear on top of
stack
327 000C2E HEADER TWOFETCH,2,'2@',DOCOLON
328 000C36 ............* DW DUP,CELLPLUS,FETCH,SWAP,FETCH,EXIT
329 000C42
330 000C42 ;C 2! x1 x2 a-addr -- store 2 cells
331 000C42 ; SWAP OVER ! CELL+ ! ;
332 000C42 ; the top of stack is stored at the lower
adrs
333 000C42 HEADER TWOSTORE,2,'2!',DOCOLON
334 000C4A ............* DW SWAP,OVER,STORE,CELLPLUS,STORE,EXIT
335 000C56
336 000C56 ;C 2DROP x1 x2 -- drop 2 cells
337 000C56 ; DROP DROP ;
338 000C56 HEADER TWODROP,5,'2DROP',DOCOLON
339 000C62 ............ DW DROP,DROP,EXIT
340 000C68
341 000C68 ;C 2DUP x1 x2 -- x1 x2 x1 x2 dup top 2
cells
342 000C68 ; OVER OVER ;
343 000C68 HEADER TWODUP,4,'2DUP',DOCOLON
344 000C72 ............ DW OVER,OVER,EXIT
345 000C78
346 000C78 ;C 2SWAP x1 x2 x3 x4 -- x3 x4 x1 x2 per
diagram
347 000C78 ; ROT >R ROT R> ;
348 000C78 HEADER TWOSWAP,5,'2SWAP',DOCOLON
349 000C84 ............* DW ROT,TOR,ROT,RFROM,EXIT
350 000C8E
351 000C8E ;C 2OVER x1 x2 x3 x4 -- x1 x2 x3 x4 x1
x2
352 000C8E ; >R >R 2DUP R> R> 2SWAP ;
353 000C8E HEADER TWOOVER,5,'2OVER',DOCOLON
354 000C9A ............* DW TOR,TOR,TWODUP,RFROM,RFROM
355 000CA4 ........ DW TWOSWAP,EXIT
356 000CA8
357 000CA8 ; INPUT/OUTPUT =================================
=
358 000CA8
359 000CA8 ;C COUNT c-addr1 -- c-addr2 u counted->adr/le
n
360 000CA8 ; DUP CHAR+ SWAP C@ ;
361 000CA8 HEADER COUNT,5,'COUNT',DOCOLON
362 000CB4 ............* DW DUP,CHARPLUS,SWAP,CFETCH,EXIT
363 000CBE
364 000CBE ;C CR -- output newline
365 000CBE ; 0D EMIT 0A EMIT ;
366 000CBE HEADER CR,2,'CR',DOCOLON
367 000CC6 ....0D00....* DW lit,0dh,EMIT,lit,0ah,EMIT,EXIT
368 000CD4
369 000CD4 ;C SPACE -- output a space
370 000CD4 ; BL EMIT ;
371 000CD4 HEADER SPACE,5,'SPACE',DOCOLON
372 000CE0 ............ DW BLANK,EMIT,EXIT
373 000CE6
374 000CE6 ;C SPACES n -- output n spaces
375 000CE6 ; BEGIN DUP WHILE SPACE 1- REPEAT DROP
;
376 000CE6 HEADER SPACES,6,'SPACES',DOCOLON
377 000CF2 ........ SPCS1: DW DUP,qbran
378 000CF6 DEST SPCS2
379 000CF8 ............ DW SPACE,ONEMINUS,bran
380 000CFE DEST SPCS1
381 000D00 ........ SPCS2: DW DROP,EXIT
382 000D04
383 000D04 ;Z umin u1 u2 -- u unsigned minimum
384 000D04 ; 2DUP U> IF SWAP THEN DROP ;
385 000D04 HEADER UMIN,4,'UMIN',DOCOLON
386 000D0E ............ DW TWODUP,UGREATER,qbran
387 000D14 DEST UMIN1
388 000D16 .... DW SWAP
389 000D18 ........ UMIN1: DW DROP,EXIT
390 000D1C
391 000D1C ;Z umax u1 u2 -- u unsigned maximum
392 000D1C ; 2DUP U< IF SWAP THEN DROP ;
393 000D1C HEADER UMAX,4,'UMAX',DOCOLON
394 000D26 ............ DW TWODUP,ULESS,qbran
395 000D2C DEST UMAX1
396 000D2E .... DW SWAP
397 000D30 ........ UMAX1: DW DROP,EXIT
398 000D34
399 000D34 ;C ACCEPT c-addr +n -- +n' get line from
term'l
400 000D34 ; OVER + 1- OVER -- sa ea a
401 000D34 ; BEGIN KEY -- sa ea a c
402 000D34 ; DUP 0D <> WHILE
403 000D34 ; DUP EMIT -- sa ea a c
404 000D34 ; DUP 8 = IF DROP 1- >R OVER R>
UMAX
405 000D34 ; ELSE OVER C! 1+ OVER UMIN
406 000D34 ; THEN -- sa ea a
407 000D34 ; REPEAT -- sa ea a c
408 000D34 ; DROP NIP SWAP - ;
409 000D34 HEADER ACCEPT,6,'ACCEPT',DOCOLON
410 000D40 ............* DW OVER,PLUS,ONEMINUS,OVER
411 000D48 ACC1: ; DW KEY,DUP,lit,0DH,NOTEQUAL,qbran
412 000D48 .... DW KEY
413 000D4A ........0D00* DW DUP,lit,0DH,NOTEQUAL ; ( -- c f )
CR
414 000D52 ; DW OVER,lit,0AH,NOTEQUAL ; ( -- c f f )
LF
415 000D52 ; DW ANDD
416 000D52 .... DW qbran
417 000D54 DEST ACC5
418 000D56 ........ DW DUP,EMIT
419 000D5A ; DW DUP,STORELEDS ; testing
420 000D5A ........0800* DW DUP,lit,8,EQUAL,qbran ;mk BS
received?
421 000D64 DEST ACC3
422 000D66 ............* DW DROP,ONEMINUS,TOR,OVER,RFROM,UMAX ;mk
backspace handling
423 000D72 ........0800* DW SPACE,lit,8,EMIT ;mk $08 == BS (for
tera term and
hyterterminal)
424 000D7A .... DW bran
425 000D7C DEST ACC4
426 000D7E ............*ACC3: DW OVER,CSTORE,ONEPLUS,OVER,UMIN
427 000D88 .... ACC4: DW bran
428 000D8A DEST ACC1
429 000D8C ............*ACC5: DW DROP,NIP,SWAP,MINUS,EXIT
430 000D96
431 000D96 ;C TYPE c-addr +n -- type line to
term'l
432 000D96 ; ?DUP IF
433 000D96 ; OVER + SWAP DO I C@ EMIT LOOP
434 000D96 ; ELSE DROP THEN ;
435 000D96 HEADER TYP,4,'TYPE',DOCOLON
436 000DA0 ........ DW QDUP,qbran
437 000DA4 DEST TYP4
438 000DA6 ............* DW OVER,PLUS,SWAP,xdo
439 000DAE ............*TYP3: DW II,CFETCH,EMIT,xloop
440 000DB6 DEST TYP3
441 000DB8 .... DW bran
442 000DBA DEST TYP5
443 000DBC .... TYP4: DW DROP
444 000DBE .... TYP5: DW EXIT
445 000DC0
446 000DC0
447 000DC0 ; HARVARD MODEL EXTENSIONS (split Code &
Data)
448 000DC0
449 000DC0 ;Z ICOUNT c-addr1 -- c-addr2 u counted->adr/le
n
450 000DC0 ; DUP CHAR+ SWAP IC@ ; from Code
space
451 000DC0 HEADER ICOUNT,6,'ICOUNT',DOCOLON
452 000DCC ............* DW DUP,CHARPLUS,SWAP,ICFETCH,EXIT
453 000DD6
454 000DD6 ;Z ITYPE c-addr +n -- type line to
term'l
455 000DD6 ; ?DUP IF from Code
space
456 000DD6 ; OVER + SWAP DO I IC@ EMIT LOOP
457 000DD6 ; ELSE DROP THEN ;
458 000DD6 HEADER ITYPE,5,'ITYPE',DOCOLON
459 000DE2 ........ DW QDUP,qbran
460 000DE6 DEST ITYP4
461 000DE8 ............* DW OVER,PLUS,SWAP,xdo
462 000DF0 ............*ITYP3: DW II,ICFETCH,EMIT,xloop
463 000DF8 DEST ITYP3
464 000DFA .... DW bran
465 000DFC DEST ITYP5
466 000DFE .... ITYP4: DW DROP
467 000E00 .... ITYP5: DW EXIT
468 000E02
469 000E02 ;Z (IS") -- c-addr u run-time code for
S"
470 000E02 ; R> ICOUNT 2DUP + ALIGNED >R ;
471 000E02 ; Harvard model, for string stored in Code
space
472 000E02 ; e.g. as used by ."
473 000E02 HEADER XISQUOTE,5,'(IS")',DOCOLON
474 000E0E ............* DW RFROM,ICOUNT,TWODUP,PLUS,ALIGNED,TOR
475 000E1A .... DW EXIT
476 000E1C
477 000E1C ;Z (S") -- c-addr u run-time code for
S"
478 000E1C ; R@ I@ get Data
address
479 000E1C ; R> CELL+ DUP IC@ CHAR+ -- Dadr Radr+2
n+1
480 000E1C ; 2DUP + ALIGNED >R -- Dadr Iadr
n+1
481 000E1C ; >R OVER R> I->D -- Dadr
482 000E1C ; COUNT ;
483 000E1C ; Harvard model, for string stored in Code
space
484 000E1C ; which is copied to Data space.
485 000E1C HEADER XSQUOTE,4,'(S")',DOCOLON
486 000E26 ........ DW RFETCH,IFETCH
487 000E2A ............* DW RFROM,CELLPLUS,DUP,ICFETCH,CHARPLUS
488 000E34 ............* DW TWODUP,PLUS,ALIGNED,TOR
489 000E3C ............* DW TOR,OVER,RFROM,ITOD,COUNT,EXIT
490 000E48
491 000E48 ;C IS" -- compile in-line
string
492 000E48 ; COMPILE (IS") [ HEX ]
493 000E48 ; 22 IWORD
494 000E48 ; IC@ 1+ ALIGNED IALLOT ; IMMEDIATE
495 000E48 ; Harvard model: string is stored in Code
space
496 000E48 IMMED ISQUOTE,3,'IS"',DOCOLON
497 000E52 ............ DW lit,XISQUOTE,COMMAXT
498 000E58 ....2200.... DW lit,22H,IWORD
499 000E5E ............* DW ICFETCH,ONEPLUS,ALIGNED,IALLOT,EXIT
500 000E68
501 000E68 ;C S" -- compile in-line
string
502 000E68 ; COMPILE (S") [ HEX ]
503 000E68 ; HERE I, data address
504 000E68 ; 22 IWORD
505 000E68 ; IC@ 1+ ALIGNED
506 000E68 ; DUP ALLOT IALLOT ; IMMEDIATE
507 000E68 ; Harvard model: string is stored in Code
space
508 000E68 IMMED SQUOTE,2,'S"',DOCOLON
509 000E70 ............ DW lit,XSQUOTE,COMMAXT
510 000E76 ............* DW HERE,ICOMMA,lit,22H,IWORD
511 000E80 ............ DW ICFETCH,ONEPLUS,ALIGNED
512 000E86 ............* DW DUP,ALLOT,IALLOT,EXIT
513 000E8E
514 000E8E ;C ." -- compile string to
print
515 000E8E ; POSTPONE IS" POSTPONE ITYPE ; IMMEDIATE
516 000E8E IMMED DOTQUOTE,2,'."',DOCOLON
517 000E96 .... DW ISQUOTE
518 000E98 ............ DW lit,ITYPE,COMMAXT
519 000E9E .... DW EXIT
520 000EA0
521 000EA0 ;Z IWORD c -- c-addr WORD to Code
space
522 000EA0 ; WORD
523 000EA0 ; IHERE TUCK OVER C@ CHAR+ D->I ;
524 000EA0 HEADER IWORD,5,'IWORD',DOCOLON
525 000EAC .... DW WORDD
526 000EAE ............*IWORD1: DW IHERE,TUCK,OVER,CFETCH
527 000EB6 ............ DW CHARPLUS,DTOI,EXIT
528 000EBC
529 000EBC ;Z IWORDC c -- c-addr maybe capitalize
WORD to Code space
530 000EBC ; WORD CAPITALIZE
531 000EBC ; IHERE TUCK OVER C@ CHAR+ D->I ;
532 000EBC ; HEADER IWORDC,6,'IWORDC',DOCOLON
533 000EBC HEADLESS IWORDC, DOCOLON
534 000EBE ........ DW WORDD, CAPITALIZE
535 000EC2 .... DW bran
536 000EC4 DEST IWORD1
537 000EC6
538 000EC6 ; SEPARATE HEADER EXTENSIONS ARE NOT USED
539 000EC6 #define HCOUNT ICOUNT
540 000EC6 #define HTYPE ITYPE
541 000EC6 #define HWORD IWORDC
542 000EC6
543 000EC6 ; NUMERIC OUTPUT ===============================
=
544 000EC6 ; Numeric conversion is done l.s.digit first,
so
545 000EC6 ; the output buffer is built backwards in
memory.
546 000EC6
547 000EC6 ; Some double-precision arithmetic operators
are
548 000EC6 ; needed to implement ANSI numeric conversion.
549 000EC6
550 000EC6 ;Z UD/MOD ud1 u2 -- u3 ud4 32/16->32
divide
551 000EC6 ; >R 0 R@ UM/MOD ROT ROT R> UM/MOD ROT
;
552 000EC6 HEADER UDSLASHMOD,6,'UD/MOD',DOCOLON
553 000ED2 ........0000* DW TOR,lit,0,RFETCH,UMSLASHMOD,ROT,ROT
554 000EE0 ............* DW RFROM,UMSLASHMOD,ROT,EXIT
555 000EE8
556 000EE8 ;Z UD* ud1 d2 -- ud3 32*16->32
multiply
557 000EE8 ; DUP >R UM* DROP SWAP R> UM* ROT +
;
558 000EE8 HEADER UDSTAR,3,'UD*',DOCOLON
559 000EF2 ............* DW DUP,TOR,UMSTAR,DROP
560 000EFA ............* DW SWAP,RFROM,UMSTAR,ROT,PLUS,EXIT
561 000F06
562 000F06 ;C HOLD char -- add char to output
string
563 000F06 ; -1 HP +! HP @ C! ;
564 000F06 HEADER HOLD,4,'HOLD',DOCOLON
565 000F10 ....FFFF....* DW lit,-1,HP,PLUSSTORE
566 000F18 ............* DW HP,FETCH,CSTORE,EXIT
567 000F20
568 000F20 ;C <# -- begin numeric conversion
569 000F20 ; PAD HP ! ; (initialize Hold
Pointer)
570 000F20 HEADER LESSNUM,2,'<#',DOCOLON
571 000F28 ............* DW PAD,HP,STORE,EXIT
572 000F30
573 000F30 ;Z >digit n -- c convert to 0..9A..Z
574 000F30 ; [ HEX ] DUP 9 > 7 AND + 30 + ;
575 000F30 HEADER TODIGIT,6,'>DIGIT',DOCOLON
576 000F3C ........0900* DW DUP,lit,9,GREATER,lit,7,ANDD,PLUS
577 000F4C ....3000....* DW lit,30H,PLUS,EXIT
578 000F54
579 000F54 ;C # ud1 -- ud2 convert 1 digit of
output
580 000F54 ; BASE @ UD/MOD ROT >digit HOLD ;
581 000F54 HEADER NUM,1,'#',DOCOLON
582 000F5C ............* DW BASE,FETCH,UDSLASHMOD,ROT,TODIGIT
583 000F66 ........ DW HOLD,EXIT
584 000F6A
585 000F6A ;C #S ud1 -- ud2 convert remaining
digits
586 000F6A ; BEGIN # 2DUP OR 0= UNTIL ;
587 000F6A HEADER NUMS,2,'#S',DOCOLON
588 000F72 ............*NUMS1: DW NUM,TWODUP,ORR,ZEROEQUAL,qbran
589 000F7C DEST NUMS1
590 000F7E .... DW EXIT
591 000F80
592 000F80 ;C #> ud1 -- c-addr u end conv., get
string
593 000F80 ; 2DROP HP @ PAD OVER - ;
594 000F80 HEADER NUMGREATER,2,'#>',DOCOLON
595 000F88 ............* DW TWODROP,HP,FETCH,PAD,OVER,MINUS,EXIT
596 000F96
597 000F96 ;C SIGN n -- add minus sign if
n<0
598 000F96 ; 0< IF 2D HOLD THEN ;
599 000F96 HEADER SIGN,4,'SIGN',DOCOLON
600 000FA0 ........ DW ZEROLESS,qbran
601 000FA4 DEST SIGN1
602 000FA6 ....2D00.... DW lit,2DH,HOLD
603 000FAC .... SIGN1: DW EXIT
604 000FAE
605 000FAE ;C U. u -- display u unsigned
606 000FAE ; <# 0 #S #> TYPE SPACE ;
607 000FAE HEADER UDOT,2,'U.',DOCOLON
608 000FB6 ........0000* DW LESSNUM,lit,0,NUMS,NUMGREATER,TYP
609 000FC2 ........ DW SPACE,EXIT
610 000FC6
611 000FC6 ;C . n -- display n signed
612 000FC6 ; <# DUP ABS 0 #S ROT SIGN #> TYPE SPACE
;
613 000FC6 HEADER DOT,1,'.',DOCOLON
614 000FCE ............* DW LESSNUM,DUP,ABBS,lit,0,NUMS
615 000FDA ............* DW ROT,SIGN,NUMGREATER,TYP,SPACE,EXIT
616 000FE6
617 000FE6 ;C DECIMAL -- set number base to
decimal
618 000FE6 ; 10 BASE ! ;
619 000FE6 HEADER DECIMAL,7,'DECIMAL',DOCOLON
620 000FF4 ....0A00....* DW lit,10,BASE,STORE,EXIT
621 000FFE
622 000FFE ;X HEX -- set number base to
hex
623 000FFE ; 16 BASE ! ;
624 000FFE HEADER HEX,3,'HEX',DOCOLON
625 001008 ....1000....* DW lit,16,BASE,STORE,EXIT
626 001012
627 001012 ; DICTIONARY MANAGEMENT ========================
=
628 001012
629 001012 ;C HERE -- addr returns dictionary
ptr
630 001012 ; DP @ ;
631 001012 HEADER HERE,4,'HERE',DOCOLON
632 00101C ............ DW DDP,FETCH,EXIT
633 001022
634 001022 ;C ALLOT n -- allocate n bytes in
dict
635 001022 ; DP +! ;
636 001022 HEADER ALLOT,5,'ALLOT',DOCOLON
637 00102E ............ DW DDP,PLUSSTORE,EXIT
638 001034
639 001034 ;C , x -- append cell to dict
640 001034 ; HERE ! 1 CELLS ALLOT ;
641 001034 HEADER COMMA,1,',',DOCOLON
642 00103C ............* DW HERE,STORE,lit,1,CELLS,ALLOT,EXIT
643 00104A
644 00104A ;C C, char -- append char to dict
645 00104A ; HERE C! 1 CHARS ALLOT ;
646 00104A HEADER CCOMMA,2,'C,',DOCOLON
647 001052 ............* DW HERE,CSTORE,lit,1,CHARS,ALLOT,EXIT
648 001060
649 001060 ; The following additional words support
the
650 001060 ; "Harvard" model, with separate address
spaces
651 001060 ; for Instructions (Code) and Data. ANSI
652 001060 ; requires DP to manage the Data space, so
a
653 001060 ; separate Instruction Dictionary Pointer,
IDP,
654 001060 ; is added to manage the Code space. Also
added:
655 001060 ; I@ IC@ I! IC! I->D D->I (in the primitives
)
656 001060 ; ITYPE ICOUNT IWORD (above)
657 001060 ; IHERE IALLOT I, IC, (below)
658 001060 ; It should be possible to convert the
Harvard
659 001060 ; implementation to a combined-code-and-data
660 001060 ; system, by equating these words to their
661 001060 ; Data-space counterparts.
662 001060
663 001060 ;C IHERE -- addr returns Code dictionary
ptr
664 001060 ; IDP @ ;
665 001060 HEADER IHERE,5,'IHERE',DOCOLON
666 00106C ............ DW IDP,FETCH,EXIT
667 001072
668 001072 ;C IALLOT n -- allocate n bytes in Code
dict
669 001072 ; IDP +! ;
670 001072 HEADER IALLOT,6,'IALLOT',DOCOLON
671 00107E ............ DW IDP,PLUSSTORE,EXIT
672 001084
673 001084 ;C I, x -- append cell to Code
dict
674 001084 ; IHERE I! 1 CELLS IALLOT ;
675 001084 HEADER ICOMMA,2,'I,',DOCOLON
676 00108C ............* DW IHERE,ISTORE,lit,1,CELLS,IALLOT,EXIT
677 00109A
678 00109A ;C IC, char -- append char to Code
dict
679 00109A ; IHERE IC! 1 CHARS IALLOT ;
680 00109A HEADER ICCOMMA,3,'IC,',DOCOLON
681 0010A4 ............* DW IHERE,ICSTORE,lit,1,CHARS,IALLOT,EXIT
682 0010B2
683 0010B2 ; SEPARATE HEADER EXTENSIONS ARE NOT USED
684 0010B2 #define HHERE IHERE
685 0010B2 #define HALLOT IALLOT
686 0010B2 #define HCOMMA ICOMMA
687 0010B2 #define HCCOMMA ICCOMMA
688 0010B2 #define HCFETCH ICFETCH
689 0010B2 #define HFETCH IFETCH
690 0010B2 #define HCSTORE ICSTORE
691 0010B2 #define HSTORE ISTORE
692 0010B2
693 0010B2 ; INTERPRETER ==================================
=
694 0010B2 ; Note that NFA>LFA, NFA>CFA, IMMED?, and
FIND
695 0010B2 ; are dependent on the structure of the
Forth
696 0010B2 ; header. This may be common across many
CPUs,
697 0010B2 ; or it may be different.
698 0010B2
699 0010B2 ;C SOURCE -- adr n current input buffer
700 0010B2 ; 'SOURCE 2@ ; length is at lower
adrs
701 0010B2 HEADER SOURCE,6,'SOURCE',DOCOLON
702 0010BE ............ DW TICKSOURCE,TWOFETCH,EXIT
703 0010C4
704 0010C4 ;X /STRING a u n -- a+n u-n trim string
705 0010C4 ; ROT OVER + ROT ROT - ;
706 0010C4 HEADER SLASHSTRING,7,'/STRING',DOCOLON
707 0010D2 ............* DW ROT,OVER,PLUS,ROT,ROT,MINUS,EXIT
708 0010E0
709 0010E0 ;Z >counted src n dst -- copy to counted
str
710 0010E0 ; 2DUP C! CHAR+ SWAP CMOVE ;
711 0010E0 HEADER TOCOUNTED,8,'>COUNTED',DOCOLON
712 0010EE ............* DW TWODUP,CSTORE,CHARPLUS,SWAP,CMOVE,EXI
T
713 0010FA
714 0010FA ;C WORD char -- c-addr n word delim'd by
char
715 0010FA ; DUP SOURCE >IN @ /STRING -- c c adr
n
716 0010FA ; DUP >R ROT SKIP -- c adr'
n'
717 0010FA ; OVER >R ROT SCAN -- adr"
n"
718 0010FA ; DUP IF CHAR- THEN skip trailing
delim.
719 0010FA ; R> R> ROT - >IN +! update >IN
offset
720 0010FA ; TUCK - -- adr'
N
721 0010FA ; HERE >counted --
722 0010FA ; HERE -- a
723 0010FA ; BL OVER COUNT + C! ; append trailing
blank
724 0010FA HEADER WORDD,4,'WORD',DOCOLON
725 001104 ............* DW DUP,SOURCE,TOIN,FETCH,SLASHSTRING
726 00110E ............* DW DUP,TOR,ROT,SKIP
727 001116 ............* DW OVER,TOR,ROT,SCAN
728 00111E ........ DW DUP,qbran
729 001122 DEST WORD1
730 001124 .... DW ONEMINUS ; char-
731 001126 ............*WORD1: DW RFROM,RFROM,ROT,MINUS,TOIN,PLUSSTORE
732 001132 ........ DW TUCK,MINUS
733 001136 ............ DW HERE,TOCOUNTED,HERE
734 00113C ............* DW BLANK,OVER,COUNT,PLUS,CSTORE,EXIT
735 001148
736 001148 ;Z NFA>LFA nfa -- lfa name adr -> link
field
737 001148 ; 3 - ;
738 001148 HEADER NFATOLFA,7,'NFA>LFA',DOCOLON
739 001156 ....0300....* DW lit,3,MINUS,EXIT
740 00115E
741 00115E ;Z NFA>CFA nfa -- cfa name adr -> code
field
742 00115E ; HCOUNT 7F AND + ALIGNED ; mask off
'smudge' bit
743 00115E HEADER NFATOCFA,7,'NFA>CFA',DOCOLON
744 00116C .... DW HCOUNT
745 00116E ....7F00....* DW lit,07FH,ANDD,PLUS,ALIGNED,EXIT
746 00117A
747 00117A ;Z IMMED? nfa -- f fetch immediate
flag
748 00117A ; 1- HC@ 1 AND 0= ; Flashable model, LSB=0
if immed
749 00117A HEADER IMMEDQ,6,'IMMED?',DOCOLON
750 001186 ............* DW ONEMINUS,HCFETCH,lit,1,ANDD,ZEROEQUAL
,EXIT
751 001194
752 001194 ;C FIND c-addr -- c-addr 0 if not found
753 001194 ;C xt 1 if immediate
754 001194 ;C xt -1 if "normal"
755 001194 ; LATEST @ BEGIN -- a nfa
756 001194 ; 2DUP OVER C@ CHAR+ -- a nfa a nfa
n+1
757 001194 ; N= -- a nfa
f
758 001194 ; DUP IF
759 001194 ; DROP
760 001194 ; NFA>LFA H@ DUP -- a link
link
761 001194 ; THEN
762 001194 ; 0= UNTIL -- a nfa OR a
0
763 001194 ; DUP IF
764 001194 ; NIP DUP NFA>CFA -- nfa xt
765 001194 ; SWAP IMMED? -- xt iflag
766 001194 ; 0= 1 OR -- xt 1/-1
767 001194 ; THEN ;
768 001194 HEADER FIND,4,'FIND',DOCOLON
769 00119E ........ DW LATEST,FETCH
770 0011A2 ............*FIND1: DW TWODUP,OVER,CFETCH,CHARPLUS
771 0011AA ............ DW NEQUAL,DUP,qbran
772 0011B0 DEST FIND2
773 0011B2 ............* DW DROP,NFATOLFA,HFETCH,DUP
774 0011BA ........ FIND2: DW ZEROEQUAL,qbran
775 0011BE DEST FIND1
776 0011C0 ........ DW DUP,qbran
777 0011C4 DEST FIND3
778 0011C6 ............ DW NIP,DUP,NFATOCFA
779 0011CC ............* DW SWAP,IMMEDQ,ZEROEQUAL,lit,1,ORR
780 0011D8 .... FIND3: DW EXIT
781 0011DA
782 0011DA ;C UPC char -- char capitalize character
783 0011DA ;
784 0011DA ; DUP [CHAR] a < OVER [CHAR] z > OR IF EXIT THEN
785 0011DA ; [ CHAR A CHAR a - ] LITERAL + ;
786 0011DA ; HEADER UPC,3,'UPC',DOCOLON
787 0011DA HEADLESS UPC, DOCOLON
788 0011DC ........6100* DW DUP, lit, 'a', LESS, OVER, lit, 'z',
GREATER
789 0011EC ........ DW ORR, qbran
790 0011F0 DEST UPC1
791 0011F2 .... DW EXIT
792 0011F4 ....E0FF.... UPC1: DW lit, 'A'-'a', PLUS
793 0011FA .... DW EXIT
794 0011FC
795 0011FC ;C CAPITALIZE c-addr -- c-addr capitalize
string
796 0011FC ;
797 0011FC ; CAPS @ IF DUP COUNT OVER + SWAP ?DO I c@ upc
I c! LOOP THEN
798 0011FC ; HEADER CAPITALIZE, 10, 'CAPITALIZE',
DOCOLON
799 0011FC HEADLESS CAPITALIZE, DOCOLON
800 0011FE ............ DW CAPS, FETCH, qbran
801 001204 DEST CAPS2
802 001206 ............* DW DUP, COUNT, OVER, PLUS, SWAP,
xdo
803 001212 ............*CAPS1: DW II, CFETCH, UPC, II, CSTORE
804 00121C .... DW xloop
805 00121E DEST CAPS1
806 001220 .... CAPS2: DW EXIT
807 001222
808 001222 ;C LITERAL x -- append numeric
literal
809 001222 ; STATE @ IF ['] LIT ,XT I, THEN ; IMMEDIATE
810 001222 ; This tests STATE so that it can also be
used
811 001222 ; interpretively. (ANSI doesn't require
this.)
812 001222 IMMED LITERAL,7,'LITERAL',DOCOLON
813 001230 ............ DW STATE,FETCH,qbran
814 001236 DEST LITER1
815 001238 ............* DW lit,lit,COMMAXT,ICOMMA
816 001240 .... LITER1: DW EXIT
817 001242
818 001242 ;Z DIGIT? c -- n -1 if c is a valid
digit
819 001242 ;Z -- x 0 otherwise
820 001242 ; [ HEX ] DUP 39 > 100 AND + silly
looking
821 001242 ; DUP 140 > 107 AND - 30 - but it
works!
822 001242 ; DUP BASE @ U< ;
823 001242 HEADER DIGITQ,6,'DIGIT?',DOCOLON
824 00124E ........3900* DW DUP,lit,39H,GREATER,lit,100H,ANDD,PLU
S
825 00125E ........4001* DW DUP,lit,140H,GREATER,lit,107H,ANDD
826 00126C ........3000* DW MINUS,lit,30H,MINUS
827 001274 ............* DW DUP,BASE,FETCH,ULESS,EXIT
828 00127E
829 00127E ;Z ?SIGN adr n -- adr' n' f get optional
sign
830 00127E ;Z advance adr/n if sign; return NZ if
negative
831 00127E ; OVER C@ -- adr n c
832 00127E ; 2C - DUP ABS 1 = AND -- +=-1, -=+1, else
0
833 00127E ; DUP IF 1+ -- +=0, -=+2
834 00127E ; >R 1 /STRING R> -- adr' n'
f
835 00127E ; THEN ;
836 00127E HEADER QSIGN,5,'?SIGN',DOCOLON
837 00128A ............* DW OVER,CFETCH,lit,2CH,MINUS,DUP,ABBS
838 001298 ....0100....* DW lit,1,EQUAL,ANDD,DUP,qbran
839 0012A4 DEST QSIGN1
840 0012A6 ............* DW ONEPLUS,TOR,lit,1,SLASHSTRING,RFROM
841 0012B2 .... QSIGN1: DW EXIT
842 0012B4
843 0012B4 ;C >NUMBER ud adr u -- ud' adr' u'
844 0012B4 ;C convert string to
number
845 0012B4 ; BEGIN
846 0012B4 ; DUP WHILE
847 0012B4 ; OVER C@ DIGIT?
848 0012B4 ; 0= IF DROP EXIT THEN
849 0012B4 ; >R 2SWAP BASE @ UD*
850 0012B4 ; R> M+ 2SWAP
851 0012B4 ; 1 /STRING
852 0012B4 ; REPEAT ;
853 0012B4 HEADER TONUMBER,7,'>NUMBER',DOCOLON
854 0012C2 ........ TONUM1: DW DUP,qbran
855 0012C6 DEST TONUM3
856 0012C8 ............ DW OVER,CFETCH,DIGITQ
857 0012CE ........ DW ZEROEQUAL,qbran
858 0012D2 DEST TONUM2
859 0012D4 ........ DW DROP,EXIT
860 0012D8 ............*TONUM2: DW TOR,TWOSWAP,BASE,FETCH,UDSTAR
861 0012E2 ............ DW RFROM,MPLUS,TWOSWAP
862 0012E8 ....0100....* DW lit,1,SLASHSTRING,bran
863 0012F0 DEST TONUM1
864 0012F2 .... TONUM3: DW EXIT
865 0012F4
866 0012F4 ;Z ?NUMBER c-addr -- n -1 string->number
867 0012F4 ;Z -- c-addr 0 if convert
error
868 0012F4 ; DUP 0 0 ROT COUNT -- ca ud adr
n
869 0012F4 ; ?SIGN >R >NUMBER -- ca ud adr'
n'
870 0012F4 ; IF R> 2DROP 2DROP 0 -- ca 0 (error)
871 0012F4 ; ELSE 2DROP NIP R>
872 0012F4 ; IF NEGATE THEN -1 -- n -1 (ok)
873 0012F4 ; THEN ;
874 0012F4 HEADER QNUMBER,7,'?NUMBER',DOCOLON
875 001302 ........0000* DW DUP,lit,0,DUP,ROT,COUNT
876 00130E ............* DW QSIGN,TOR,TONUMBER,qbran
877 001316 DEST QNUM1
878 001318 ............* DW RFROM,TWODROP,TWODROP,lit,0
879 001322 .... DW bran
880 001324 DEST QNUM3
881 001326 ............*QNUM1: DW TWODROP,NIP,RFROM,qbran
882 00132E DEST QNUM2
883 001330 .... DW NEGATE
884 001332 ....FFFF QNUM2: DW lit,-1
885 001336 .... QNUM3: DW EXIT
886 001338
887 001338 ;Z INTERPRET i*x c-addr u -- j*x
888 001338 ;Z interpret given
buffer
889 001338 ; This is a common factor of EVALUATE and
QUIT.
890 001338 ; ref. dpANS-6, 3.4 The Forth Text Interpreter
891 001338 ; 'SOURCE 2! 0 >IN !
892 001338 ; BEGIN
893 001338 ; BL WORD DUP C@ WHILE -- textadr
894 001338 ; CAPITALIZE
895 001338 ; FIND -- a 0/1/-1
896 001338 ; ?DUP IF -- xt 1/-1
897 001338 ; 1+ STATE @ 0= OR IMMED or
interp?
898 001338 ; IF EXECUTE ELSE ,XT THEN
899 001338 ; ELSE -- textadr
900 001338 ; ?NUMBER
901 001338 ; IF POSTPONE LITERAL converted
ok
902 001338 ; ELSE COUNT TYPE 3F EMIT CR ABORT
err
903 001338 ; THEN
904 001338 ; THEN
905 001338 ; REPEAT DROP ;
906 001338 HEADER INTERPRET,9,'INTERPRET',DOCOLON
907 001348 ............* DW TICKSOURCE,TWOSTORE,lit,0,TOIN,STORE
908 001354 ............*INTER1: DW BLANK,WORDD,DUP,CFETCH,qbran
909 00135E DEST INTER9
910 001360 .... DW CAPITALIZE
911 001362 ............ DW FIND,QDUP,qbran
912 001368 DEST INTER4
913 00136A ............* DW ONEPLUS,STATE,FETCH,ZEROEQUAL,ORR
914 001374 .... DW qbran
915 001376 DEST INTER2
916 001378 ........ DW EXECUTE,bran
917 00137C DEST INTER3
918 00137E .... INTER2: DW COMMAXT
919 001380 .... INTER3: DW bran
920 001382 DEST INTER8
921 001384 ........ INTER4: DW QNUMBER,qbran
922 001388 DEST INTER5
923 00138A ........ DW LITERAL,bran
924 00138E DEST INTER6
925 001390 ............*INTER5: DW COUNT,TYP,lit,3FH,EMIT,CR,ABORT
926 00139E INTER6:
927 00139E .... INTER8: DW bran
928 0013A0 DEST INTER1
929 0013A2 ........ INTER9: DW DROP,EXIT
930 0013A6
931 0013A6 ;C EVALUATE i*x c-addr u -- j*x interprt
string
932 0013A6 ; 'SOURCE 2@ >R >R >IN @ >R
933 0013A6 ; INTERPRET
934 0013A6 ; R> >IN ! R> R> 'SOURCE 2! ;
935 0013A6 HEADER EVALUATE,8,'EVALUATE',DOCOLON
936 0013B4 ............* DW TICKSOURCE,TWOFETCH,TOR,TOR
937 0013BC ............* DW TOIN,FETCH,TOR,INTERPRET
938 0013C4 ............* DW RFROM,TOIN,STORE,RFROM,RFROM
939 0013CE ............ DW TICKSOURCE,TWOSTORE,EXIT
940 0013D4
941 0013D4 #define PREFIXPROMPT 0
942 0013D4
943 0013D4 ; C DOTSTATUS -- display system status
944 0013D4 HEADLESS DOTSTATUS,DOCOLON
945 0013D6 ....1100.... DW lit,11H,EMIT ; send XON
946 0013DC .... DW CR
947 0013DE IF PREFIXPROMPT=1
948 0013DE DW XISQUOTE
949 0013DE DB 3,'OK ' ; for prefix prompt
style
950 0013DE DW ITYPE
951 0013DE ENDIF
952 0013DE .... DW EXIT
953 0013E0
954 0013E0 ; C PROMPT -- prompt user
955 0013E0 HEADLESS PROMPT,DOCOLON
956 0013E2 IF PREFIXPROMPT!=1
957 0013E2 ............* DW STATE,FETCH,ZEROEQUAL,qbran
958 0013EA DEST PROMPT1
959 0013EC .... DW XISQUOTE
960 0013EE 036F6B20 DB 3,'ok ' ; for traditional Forth
style
961 0013F2 .... DW ITYPE
962 0013F4 ENDIF
963 0013F4 .... PROMPT1:DW EXIT
964 0013F6
965 0013F6 ;C QUIT -- R: i*x -- interpret from
kbd
966 0013F6 ; L0 LP ! R0 RP! 0 STATE !
967 0013F6 ; BEGIN
968 0013F6 ; xon EMIT
969 0013F6 ; TIB DUP TIBSIZE ACCEPT
970 0013F6 ; xoff EMIT SPACE
971 0013F6 ; INTERPRET
972 0013F6 ; CR STATE @ 0= IF ." OK" THEN
973 0013F6 ; AGAIN ;
974 0013F6 HEADER QUIT,4,'QUIT',DOCOLON
975 001400 ............ DW L0,LP,STORE
976 001406 ............* DW RZERO,RPSTORE,lit,0,STATE,STORE
977 001412 .... QUIT1: DW DOTSTATUS
978 001414 ............* DW TIB,DUP,TIBSIZE,ACCEPT
979 00141C ; DW lit,13H,EMIT ; send
XOFF
980 00141C .... DW SPACE
981 00141E .... DW INTERPRET
982 001420 .... DW PROMPT
983 001422 .... DW bran
984 001424 DEST QUIT1
985 000000 PUBLIC QUITIP
986 001426 QUITIP equ QUIT+2
987 001426
988 001426
989 001426
990 001426 ;C ABORT i*x -- R: j*x -- clear stk &
QUIT
991 001426 ; S0 SP! QUIT ;
992 001426 HEADER ABORT,5,'ABORT',DOCOLON
993 001432 ............ DW S0,SPSTORE,QUIT ; QUIT never
returns
994 001438
995 001438 ;Z ?ABORT f c-addr u -- abort & print
msg
996 001438 ; ROT IF ITYPE ABORT THEN 2DROP ;
997 001438 HEADER QABORT,6,'?ABORT',DOCOLON
998 001444 ........ DW ROT,qbran
999 001448 DEST QABO1
1000 00144A ........ DW ITYPE,ABORT
1001 00144E ........ QABO1: DW TWODROP,EXIT
1002 001452
1003 001452 ;C ABORT" i*x 0 -- i*x R: j*x -- j*x
x1=0
1004 001452 ;C i*x x1 -- R: j*x --
x1<>0
1005 001452 ; POSTPONE IS" POSTPONE ?ABORT ; IMMEDIATE
1006 001452 IMMED ABORTQUOTE,6,'ABORT"',DOCOLON
1007 00145E .... DW ISQUOTE
1008 001460 ............ DW lit,QABORT,COMMAXT
1009 001466 .... DW EXIT
1010 001468
1011 001468 ;C ' -- xt find word in dictionary
1012 001468 ; BL WORD CAPITALIZE FIND
1013 001468 ; 0= ABORT" ?" ;
1014 001468 HEADER TICK,1,27h,DOCOLON
1015 001470 ............* DW BLANK,WORDD,CAPITALIZE,FIND,ZEROEQUAL
,XISQUOTE
1016 00147C 013F DB 1,'?'
1017 00147E ........ DW QABORT,EXIT
1018 001482
1019 001482 ;C CHAR -- char parse ASCII
character
1020 001482 ; BL WORD 1+ C@ ;
1021 001482 HEADER CHARR,4,'CHAR',DOCOLON
1022 00148C ............* DW BLANK,WORDD,ONEPLUS,CFETCH,EXIT
1023 001496
1024 001496 ;C [CHAR] -- compile character
literal
1025 001496 ; CHAR ['] LIT ,XT I, ; IMMEDIATE
1026 001496 IMMED BRACCHAR,6,'[CHAR]',DOCOLON
1027 0014A2 .... DW CHARR
1028 0014A4 ............ DW lit,lit,COMMAXT
1029 0014AA ........ DW ICOMMA,EXIT
1030 0014AE
1031 0014AE ;C ( -- skip input until
)
1032 0014AE ; [ HEX ] 29 WORD DROP ; IMMEDIATE
1033 0014AE IMMED PAREN,1,'(',DOCOLON
1034 0014B6 ....2900....* DW lit,29H,WORDD,DROP,EXIT
1035 0014C0
1036 0014C0 ; COMPILER =====================================
=
1037 0014C0
1038 0014C0 ;Z HEADER -- create a Forth word
header
1039 0014C0 ; LATEST @ H, 0FF HC, link & IMMED
field
1040 0014C0 ; HHERE LATEST ! new "latest"
link
1041 0014C0 ; BL HWORD HC@ 1+ HALLOT name field
1042 0014C0 ; ALIGN ;
1043 0014C0 ; Separate headers model.
1044 0014C0 HEADER HEADR,6,'HEADER',DOCOLON
1045 0014CC ............ DW LATEST,FETCH,HCOMMA ; link
1046 0014D2 ....FF00.... DW lit,0FFh,HCCOMMA ; immediate
flag - see
note
below
1047 0014D8 ............ DW HHERE,LATEST,STORE
1048 0014DE ............* DW BLANK,HWORD,HCFETCH,ONEPLUS,HALLOT
1049 0014E8 ........ DW ALIGNN,EXIT ; MSP430: headers in I
space must be
aligned
1050 0014EC ; Note for Flashable MSP430: when compiling to
RAM, we need to set
1051 0014EC ; the immediate byte to 0FFH. When compiling to
Flash, the word IC!
1052 0014EC ; will not write 0FFH to erased Flash (because
the byte is already 0FFH).
1053 0014EC ; Thus we can write this byte at a later time
(with IMMEDIATE).
1054 0014EC
1055 0014EC ;Z ) -- run-time action of
DOES>
1072 00151E ; R> adrs of headless DOES>
def'n
1073 00151E ; LATEST @ NFA>CFA code field to fix
up
1074 00151E ; !CF ;
1075 00151E HEADER XDOES,7,'(DOES>)',DOCOLON
1076 00152C ............* DW RFROM,LATEST,FETCH,NFATOCFA,STORECF
1077 001536 .... DW EXIT
1078 001538
1079 001538 ;C DOES> -- change action of latest
def'n
1080 001538 ; COMPILE (DOES>)
1081 001538 ; dodoes ,JMP ; IMMEDIATE
1082 001538 ; Note that MSP430 uses a JMP, not a CALL, to
DODOES.
1083 001538 IMMED DOES,5,'DOES>',DOCOLON
1084 001544 ............ DW lit,XDOES,COMMAXT
1085 00154A ............* DW lit,dodoes,COMMAJMP,EXIT
1086 001552
1087 001552 ;C RECURSE -- recurse current definition
1088 001552 ; LATEST @ NFA>CFA ,XT ; IMMEDIATE
1089 001552 ; NEWEST @ NFA>CFA ,XT ; IMMEDIATE
Flashable
1090 001552 IMMED RECURSE,7,'RECURSE',DOCOLON
1091 001560 ............* DW NEWEST,FETCH,NFATOCFA,COMMAXT,EXIT
1092 00156A
1093 00156A ;C [ -- enter interpretive
state
1094 00156A ; 0 STATE ! ; IMMEDIATE
1095 00156A IMMED LEFTBRACKET,1,'[',DOCOLON
1096 001572 ....0000....* DW lit,0,STATE,STORE,EXIT
1097 00157C
1098 00157C ;C ] -- enter compiling state
1099 00157C ; -1 STATE ! ;
1100 00157C HEADER RIGHTBRACKET,1,']',DOCOLON
1101 001584 ....FFFF....* DW lit,-1,STATE,STORE,EXIT
1102 00158E
1103 00158E ;Z HIDE -- "hide" latest definition
Flashable
1104 00158E ; LATEST @ DUP NEWEST ! NFA>LFA H@ LATEST !
;
1105 00158E HEADER HIDE,4,'HIDE',DOCOLON
1106 001598 ............* DW LATEST,FETCH,DUP,NEWEST,STORE
1107 0015A2 ............* DW NFATOLFA,HFETCH,LATEST,STORE,EXIT
1108 0015AC
1109 0015AC ;Z REVEAL -- "reveal" latest definition
Flashable
1110 0015AC ; NEWEST @ LATEST ! ;
1111 0015AC HEADER REVEAL,6,'REVEAL',DOCOLON
1112 0015B8 ............* DW NEWEST,FETCH,LATEST,STORE,EXIT
1113 0015C2
1114 0015C2 ;C IMMEDIATE -- make last def'n immediate
1115 0015C2 ; 0FE LATEST @ 1- HC! ; set Flashable
immediate flag
1116 0015C2 HEADER IMMEDIATE,9,'IMMEDIATE',DOCOLON
1117 0015D2 ....FE00....* DW lit,0FEh,LATEST,FETCH,ONEMINUS,HCSTOR
E
1118 0015DE .... DW EXIT
1119 0015E0
1120 0015E0 ;C : -- begin a colon definition
1121 0015E0 ; DUP CELL+ >R @ ,XT ;
1168 001652 ; The phrase ['] xxx ,XT appears so often
that
1169 001652 ; this word was created to combine the
actions
1170 001652 ; of LIT and ,XT. It takes an inline literal
1171 001652 ; execution token and appends it to the
dict.
1172 001652 ; HEADER COMPILE,7,'COMPILE',DOCOLON
1173 001652 ; DW RFROM,DUP,CELLPLUS,TOR
1174 001652 ; DW FETCH,COMMAXT,EXIT
1175 001652 ; N.B.: not used in the current implementation
1176 001652
1177 001652 ; CONTROL STRUCTURES ===========================
=
1178 001652
1179 001652 ;C IF -- adrs conditional forward
branch
1180 001652 ; ['] qbran ,BRANCH IHERE ,NONE ;
Flashable
1181 001652 ; IMMEDIATE
1182 001652 IMMED IFF,2,'IF',DOCOLON
1183 00165A ............ DW lit,qbran,COMMABRANCH
1184 001660 ............ DW IHERE,COMMANONE,EXIT
1185 001666
1186 001666 ;C THEN adrs -- resolve forward
branch
1187 001666 ; IHERE SWAP !DEST ; IMMEDIATE
1188 001666 IMMED THEN,4,'THEN',DOCOLON
1189 001670 ............* DW IHERE,SWAP,STOREDEST,EXIT
1190 001678
1191 001678 ;C ELSE adrs1 -- adrs2 branch for
IF..ELSE
1192 001678 ; ['] branch ,BRANCH IHERE ,NONE
Flashable
1193 001678 ; SWAP POSTPONE THEN ; IMMEDIATE
1194 001678 IMMED ELSS,4,'ELSE',DOCOLON
1195 001682 ............ DW lit,bran,COMMABRANCH
1196 001688 ........ DW IHERE,COMMANONE
1197 00168C ............ DW SWAP,THEN,EXIT
1198 001692
1199 001692 ;C BEGIN -- adrs target for bwd.
branch
1200 001692 ; IHERE ; IMMEDIATE
1201 001692 IMMED BEGIN,5,'BEGIN',DOCOLON
1202 00169E ........ DW IHERE,EXIT
1203 0016A2
1204 0016A2 ;C UNTIL adrs -- conditional backward
branch
1205 0016A2 ; ['] qbran ,BRANCH ,DEST ; IMMEDIATE
1206 0016A2 ; conditional backward branch
1207 0016A2 IMMED UNTIL,5,'UNTIL',DOCOLON
1208 0016AE ............ DW lit,qbran,COMMABRANCH
1209 0016B4 ........ DW COMMADEST,EXIT
1210 0016B8
1211 0016B8 ;X AGAIN adrs -- uncond'l backward
branch
1212 0016B8 ; ['] branch ,BRANCH ,DEST ; IMMEDIATE
1213 0016B8 ; unconditional backward branch
1214 0016B8 IMMED AGAIN,5,'AGAIN',DOCOLON
1215 0016C4 ............ DW lit,bran,COMMABRANCH
1216 0016CA ........ DW COMMADEST,EXIT
1217 0016CE
1218 0016CE ;C WHILE adrs1 -- adrs2 adrs1
1219 0016CE ; branch for WHILE
loop
1220 0016CE ; POSTPONE IF SWAP ; IMMEDIATE
1221 0016CE IMMED WHILE,5,'WHILE',DOCOLON
1222 0016DA ............ DW IFF,SWAP,EXIT
1223 0016E0
1224 0016E0 ;C REPEAT adrs2 adrs1 -- resolve WHILE
loop
1225 0016E0 ; POSTPONE AGAIN POSTPONE THEN ; IMMEDIATE
1226 0016E0 IMMED REPEAT,6,'REPEAT',DOCOLON
1227 0016EC ............ DW AGAIN,THEN,EXIT
1228 0016F2
1229 0016F2 ;Z >L x -- L: -- x move to leave
stack
1230 0016F2 ; CELL LP +! LP @ ! ; (L stack grows
up)
1231 0016F2 HEADER TOL,2,'>L',DOCOLON
1232 0016FA ............* DW CELL,LP,PLUSSTORE,LP,FETCH,STORE,EXIT
1233 001708
1234 001708 ;Z L> -- x L: x -- move from leave
stack
1235 001708 ; LP @ @ CELL NEGATE LP +! ;
1236 001708 HEADER LFROM,2,'L>',DOCOLON
1237 001710 ............ DW LP,FETCH,FETCH
1238 001716 ............* DW CELL,NEGATE,LP,PLUSSTORE,EXIT
1239 001720
1240 001720 ;C DO -- adrs L: -- 0
1241 001720 ; ['] xdo ,XT IHERE target for bwd
branch
1242 001720 ; 0 >L ; IMMEDIATE marker for
LEAVEs
1243 001720 IMMED DO,2,'DO',DOCOLON
1244 001728 ............* DW lit,xdo,COMMAXT,IHERE
1245 001730 ....0000....* DW lit,0,TOL,EXIT
1246 001738
1247 001738 ;Z ENDLOOP adrs xt -- L: 0 a1 a2 .. aN
--
1248 001738 ; ,BRANCH ,DEST backward
loop
1249 001738 ; BEGIN L> ?DUP WHILE POSTPONE THEN REPEAT
;
1250 001738 ; resolve
LEAVEs
1251 001738 ; This is a common factor of LOOP and +LOOP.
1252 001738 HEADER ENDLOOP,7,'ENDLOOP',DOCOLON
1253 001746 ........ DW COMMABRANCH,COMMADEST
1254 00174A ............ LOOP1: DW LFROM,QDUP,qbran
1255 001750 DEST LOOP2
1256 001752 ........ DW THEN,bran
1257 001756 DEST LOOP1
1258 001758 .... LOOP2: DW EXIT
1259 00175A
1260 00175A ;C LOOP adrs -- L: 0 a1 a2 .. aN --
1261 00175A ; ['] xloop ENDLOOP ; IMMEDIATE
1262 00175A IMMED LOO,4,'LOOP',DOCOLON
1263 001764 ............* DW lit,xloop,ENDLOOP,EXIT
1264 00176C
1265 00176C ;C +LOOP adrs -- L: 0 a1 a2 .. aN --
1266 00176C ; ['] xplusloop ENDLOOP ; IMMEDIATE
1267 00176C IMMED PLUSLOOP,5,'+LOOP',DOCOLON
1268 001778 ............* DW lit,xplusloop,ENDLOOP,EXIT
1269 001780
1270 001780 ;C LEAVE -- L: -- adrs
1271 001780 ; ['] UNLOOP ,XT
1272 001780 ; ['] branch ,BRANCH IHERE ,NONE >L
1273 001780 ; ; IMMEDIATE unconditional forward
branch
1274 001780 IMMED LEAV,5,'LEAVE',DOCOLON
1275 00178C ............ DW lit,UNLOOP,COMMAXT
1276 001792 ............ DW lit,bran,COMMABRANCH
1277 001798 ............* DW IHERE,COMMANONE,TOL,EXIT
1278 0017A0
1279 0017A0 ;C FOR -- addr
1280 0017A0 ; ['] >R ,XT [COMPILE] BEGIN
1281 0017A0 IMMED FOR,3,'FOR',DOCOLON
1282 0017AA ............* DW lit,TOR,COMMAXT,BEGIN,EXIT
1283 0017B4
1284 0017B4 ;C NEXT addr --
1285 0017B4 ; ['] (next) ,XT ,DEST ;
1286 0017B4 IMMED NEXTT,4,'NEXT',DOCOLON
1287 0017BE ............* DW lit,xnext,COMMAXT,COMMADEST,EXIT
1288 0017C8
1289 0017C8 ; OTHER OPERATIONS =============================
=
1290 0017C8
1291 0017C8 ;X WITHIN n1|u1 n2|u2 n3|u3 -- f n2<=n1R - R> U< ; per ANS
document
1293 0017C8 HEADER WITHIN,6,'WITHIN',DOCOLON
1294 0017D4 ............* DW OVER,MINUS,TOR,MINUS,RFROM,ULESS,EXIT
1295 0017E2
1296 0017E2 ;C MOVE addr1 addr2 u -- smart move
1297 0017E2 ; VERSION FOR 1 ADDRESS UNIT = 1
CHAR
1298 0017E2 ; >R 2DUP SWAP DUP R@ + -- ... dst src
src+n
1299 0017E2 ; WITHIN IF R> CMOVE> src <= dst <
src+n
1300 0017E2 ; ELSE R> CMOVE THEN ;
otherwise
1301 0017E2 HEADER MOVE,4,'MOVE',DOCOLON
1302 0017EC ............* DW TOR,TWODUP,SWAP,DUP,RFETCH,PLUS
1303 0017F8 ........ DW WITHIN,qbran
1304 0017FC DEST MOVE1
1305 0017FE ............ DW RFROM,CMOVEUP,bran
1306 001804 DEST MOVE2
1307 001806 ........ MOVE1: DW RFROM,CMOVE
1308 00180A .... MOVE2: DW EXIT
1309 00180C
1310 00180C ;C DEPTH -- +n number of items on
stack
1311 00180C ; SP@ S0 SWAP - 2/ ; 16-BIT VERSION!
1312 00180C HEADER DEPTH,5,'DEPTH',DOCOLON
1313 001818 ............* DW SPFETCH,S0,SWAP,MINUS,TWOSLASH,EXIT
1314 001824
1315 001824 ;C ENVIRONMENT? c-addr u -- false system
query
1316 001824 ; -- i*x true
1317 001824 ; 2DROP 0 ; the minimal definition!
1318 001824 HEADER ENVIRONMENTQ,12,'ENVIRONMENT?',DOCOL
ON
1319 001836 ........0000* DW TWODROP,lit,0,EXIT
1320 00183E
1321 00183E ;U UTILITY WORDS =====================
1322 00183E
1323 00183E ;Z NOOP -- do nothing
1324 00183E HEADER NOOP,4,'NOOP',DOCOLON
1325 001848 .... DW EXIT
1326 00184A
1327 00184A ;Z FLALIGNED a -- a' align IDP to flash
boundary
1328 00184A ; $200 OVER - $1FF AND + ;
1329 00184A HEADER FLALIGNED,9,'FLALIGNED',DOCOLON
1330 00185A ....0002....* DW lit,0200h,OVER,MINUS,lit,01FFh,ANDD,P
LUS,EXIT
1331 00186C
1332 00186C ;X MARKER -- create word to restore
dictionary
1333 00186C ; LATEST @ IHERE HERE
1334 00186C ; IHERE FLALIGNED IDP ! align new word to
flash boundary
1335 00186C ; DUP I@
1337 00186C ; SWAP CELL+ DUP I@
1338 00186C ; SWAP CELL+ I@ fetch saved -- dp
idp latest
1339 00186C ; OVER FLALIGNED IHERE OVER - FLERASE erase
Flash from saved to IHERE
1340 00186C ; LATEST ! IDP ! DP ! ;
1341 00186C HEADER MARKER,6,'MARKER',DOCOLON
1342 001878 ............* DW LATEST,FETCH,IHERE,HERE
1343 001880 ............* DW IHERE,FLALIGNED,IDP,STORE
1344 001888 ............* DW BUILDS,ICOMMA,ICOMMA,ICOMMA,XDOES
1345 001892 3040.... MOV #dodoes,PC ; long direct jump
to DODOES
1346 001896 ........ DW DUP,IFETCH
1347 00189A ............* DW SWAP,CELLPLUS,DUP,IFETCH
1348 0018A2 ............ DW SWAP,CELLPLUS,IFETCH
1349 0018A8 ............* DW OVER,FLALIGNED,IHERE,OVER,MINUS,FLERA
SE
1350 0018B4 ............* DW LATEST,STORE,IDP,STORE,DDP,STORE,EXIT
1351 0018C2
1352 0018C2 ;X WORDS -- list all words in
dict.
1353 0018C2 ; LATEST @ BEGIN
1354 0018C2 ; DUP HCOUNT 7F AND HTYPE SPACE
1355 0018C2 ; NFA>LFA H@
1356 0018C2 ; DUP 0= UNTIL
1357 0018C2 ; DROP ;
1358 0018C2 HEADER WORDS,5,'WORDS',DOCOLON
1359 0018CE ........ DW LATEST,FETCH
1360 0018D2 ............*WDS1: DW DUP,HCOUNT,lit,07FH,ANDD,HTYPE,SPACE
1361 0018E0 ........ DW NFATOLFA,HFETCH
1362 0018E4 ............ DW DUP,ZEROEQUAL,qbran
1363 0018EA DEST WDS1
1364 0018EC ........ DW DROP,EXIT
1365 0018F0
1366 0018F0 ;X U.R u n -- display u unsigned in
n width
1367 0018F0 ; >R <# 0 #S #> R> OVER - 0 MAX SPACES TYPE
;
1368 0018F0 HEADER UDOTR,3,'U.R',DOCOLON
1369 0018FA ............* DW TOR,LESSNUM,lit,0,NUMS,NUMGREATER
1370 001906 ............* DW RFROM,OVER,MINUS,lit,0,MAX,SPACES,TYP
,EXIT
1371 001918
1372 001918 ;X DUMP adr n -- dump memory
1373 001918 ; OVER + SWAP DO
1374 001918 ; CR I 4 U.R SPACE SPACE
1375 001918 ; I $10 + I DO I C@ 3 U.R LOOP SPACE
SPACE
1376 001918 ; I $10 + I DO I C@ $7F AND $7E MIN BL MAX
EMIT LOOP
1377 001918 ; 10 +LOOP ;
1378 001918 HEADER DUMP,4,'DUMP',DOCOLON
1379 001922 ............* DW OVER,PLUS,SWAP,xdo
1380 00192A ............*LDUMP1: DW CR,II,lit,4,UDOTR,SPACE,SPACE
1381 001938 ........1000* DW II,lit,10h,PLUS,II,xdo
1382 001944 ............*LDUMP2: DW II,CFETCH,lit,3,UDOTR,xloop
1383 001950 DEST LDUMP2
1384 001952 ........ DW SPACE,SPACE
1385 001956 ........1000* DW II,lit,10h,PLUS,II,xdo
1386 001962 ............*LDUMP3: DW II,CFETCH,lit,7Fh,ANDD,lit,7Eh,MIN,BL
ANK,MAX,EMIT,xloop
1387 00197A DEST LDUMP3
1388 00197C ....1000.... DW lit,10h,xplusloop
1389 001982 DEST LDUMP1
1390 001984 .... DW EXIT
1391 001986
1392 001986 ;X .S -- print stack contents
1393 001986 ; [char] < EMIT DEPTH . BS [char] > EMIT
1394 001986 ; SP@ S0 < IF
1395 001986 ; SP@ S0 2 - DO I @ U. -2 +LOOP
1396 001986 ; THEN ;
1397 001986 HEADER DOTS,2,'.S',DOCOLON
1398 00198E ;mk gforth style
1399 00198E ....3C00.... DW lit,$3C,EMIT
1400 001994 ........ DW DEPTH,DOT
1401 001998 ....0800....* DW lit,$08,EMIT,lit,$3E,EMIT,SPACE
1402 0019A6 ;/mk
1403 0019A6 ............* DW SPFETCH,S0,LESS,qbran
1404 0019AE DEST DOTS2
1405 0019B0 ............* DW SPFETCH,S0,lit,2,MINUS,xdo
1406 0019BC ............*DOTS1: DW II,FETCH,UDOT,lit,-2,xplusloop
1407 0019C8 DEST DOTS1
1408 0019CA .... DOTS2: DW EXIT
1409 0019CC
1410 0019CC
1411 0019CC ;U ccrc n c -- n' crc process
byte
1412 0019CC ; 8 LSHIFT XOR
1413 0019CC ; 8 0 DO ( n' )
1414 0019CC ; DUP 1 LSHIFT SWAP 8000 AND 0= INVERT 1021
( CRC-16 ) AND XOR
1415 0019CC ; LOOP
1416 0019CC ; FFFF AND ;
1417 0019CC ; HEADER CCRC,4,'ccrc',DOCODE
1418 0019CC HEADLESS CCRC,DOCODE
1419 0019CE 37F0FF00 AND #00FFh,TOS
1420 0019D2 8710 SWPB TOS
1421 0019D4 37E4 XOR @PSP+,TOS
1422 0019D6 3642 MOV #8,W
1423 0019D8 0757 ccrc1: RLA TOS
1424 0019DA 0228 JNC ccrc2
1425 0019DC 37E02110 XOR #01021h,TOS
1426 0019E0 1683 ccrc2: DEC W
1427 0019E2 FA23 JNZ ccrc1
1428 0019E4 NEXT
1429 0019E8
1430 0019E8 ;U crc n addr len -- n' crc process
string
1431 0019E8 ; dup IF over + swap DO ( n ) I C@ ccrc LOOP
ELSE 2drop THEN ;
1432 0019E8 HEADER CRC,3,'CRC',DOCOLON
1433 0019F2 ........ DW DUP,qbran
1434 0019F6 DEST pcrc2
1435 0019F8 ............* DW OVER,PLUS,SWAP,xdo
1436 001A00 ............*pcrc1: DW II,CFETCH,CCRC, xloop
1437 001A08 DEST pcrc1
1438 001A0A .... DW bran
1439 001A0C DEST pcrc3
1440 001A0E .... pcrc2: DW TWODROP
1441 001A10 .... pcrc3: DW EXIT
1442 001A12
1443 001A12
1444 001A12 ;U STARTUP WORDS ===============================
================================
1445 001A12
1446 001A12 ;Z ITHERE -- adr find first free flash
cell
1447 001A12 ; MEMTOP BEGIN 1-
1448 001A12 ; DUP C@ FF <>
1449 001A12 ; OVER FL0 < OR UNTIL 1+ ;
1450 001A12 HEADER ITHERE,6,'ITHERE',DOCOLON
1451 001A1E .... DW MEMTOP
1452 001A20 ............*ih1 DW ONEMINUS,DUP,CFETCH,lit,$FF,NOTEQUAL
1453 001A2C ........00C0* DW OVER,lit,FLASHSTART,LESS,ORR,qbran
1454 001A38 DEST ih1
1455 001A3A ........ DW ONEPLUS,EXIT
1456 001A3E
1457 001A3E ;U APPCRC -- crc CRC of APP-dictionary
1458 001A3E ; 0 MEMBOT ITHERE OVER - (crc APPU0 #INIT
(crc ;
1459 001A3E ; HEADER APPCRC,6,'APPCRC',DOCOLON
1460 001A3E HEADLESS APPCRC,DOCOLON
1461 001A40 ....0000 DW lit,0
1462 001A44 ....00C0....* DW lit,FLASHSTART,ITHERE,OVER,MINUS,CRC
1463 001A50 ............* DW APPU0,NINIT,CRC,EXIT
1464 001A58
1465 000000 EXTERN crcval
1466 001A58
1467 001A58 ;U VALID? -- f check if user app crc
matches infoB
1468 001A58 ; APPCRC crcval I@ = ;
1469 001A58 ; HEADER VALIDQ,6,'VALID?',DOCOLON
1470 001A58 HEADLESS VALIDQ,DOCOLON
1471 001A5A ............* DW APPCRC,lit,crcval,IFETCH,EQUAL,EXIT
1472 001A66
1473 001A66 ;U SAVE -- save user area to infoB
1474 001A66 ; InfoB [ 63 2 + ] Literal FLERASE
1475 001A66 ; U0 APPU0 #INIT D->I
1476 001A66 ; APPCRC [ crcval ] Literal I! ;
1477 001A66 HEADER SAVE,4,'SAVE',DOCOLON
1478 001A70 ........4100* DW INFOB,lit,63+2,FLERASE
1479 001A78 ............* DW U0,APPU0,NINIT,DTOI
1480 001A80 ............* DW APPCRC,lit,crcval,ISTORE
1481 001A88 .... DW EXIT
1482 001A8A
1483 00018E CORREST EQU 018Eh
1484 000186 CORPOWERON EQU 0186h
1485 001A8A
1486 001A8A ;Z BOOT -- boot system
1487 001A8A HEADER BOOT,4,'BOOT',DOCOLON
1488 001A94 .... DW DOTVER
1489 001A96 ............ DW S2,cget,qbran
1490 001A9C DEST boot1
1491 001A9E ........ DW VALIDQ,qbran
1492 001AA2 DEST invalid
1493 001AA4 .... valid: DW COLD ; valid infoB and dictionary
1494 001AA6 ............*invalid:DW COR,FETCH,lit,CORPOWERON,NOTEQUAL,qbr
an
1495 001AB2 DEST boot1
1496 001AB4 reset: ; reset and invalid infoB
1497 001AB4 ............* DW LATEST,FETCH,lit,FLASHSTART,ITHERE,WI
THIN,qbran ; check RAM latest
1498 001AC2 DEST boot1
1499 001AC4 .... DW WARM ; invalid infoB but seemingly
valid RAM
1500 001AC6 .... boot1: DW WIPE ; invalid infoB but power on
or RAM invalid
1501 001AC8
1502 000000 PUBLIC BOOTIP ; used to init IP register.
1503 001AC8 BOOTIP equ BOOT+2
1504 001AC8
1505 001AC8 ;Z WARM -- use user area from RAM
(hopefully intact)
1506 001AC8 HEADER WARM,4,'WARM',DOCOLON
1507 001AD2 .... DW XISQUOTE
1508 001AD4 05 DB (warm1-warm0)
1509 001AD5 5761726D warm0: DB 'Warm'
1510 001AD9 00 EVEN
1511 001ADA .... warm1: DW ITYPE
1512 001ADC .... DW ABORT
1513 001ADE
1514 001ADE ;U .COLD -- display COLD message
1515 001ADE HEADLESS DOTCOLD,DOCOLON
1516 001AE0 .... DW XISQUOTE
1517 001AE2 05 DB (dotcold1-dotcold0)
1518 001AE3 436F6C64 dotcold0:DB 'Cold'
1519 001AE7 00 EVEN
1520 001AE8 .... dotcold1:DW ITYPE
1521 001AEA .... DW EXIT
1522 001AEC
1523 001AEC PUBLIC DOTCOLD
1524 001AEC
1525 001AEC ;Z COLD -- set user area to latest
application
1526 001AEC HEADER COLD,4,'COLD',DOCOLON
1527 001AF6 ............* DW APPU0,U0,NINIT,ITOD ; use application
user area
1528 001AFE ............ DW APP,FETCH,EXECUTE ; AUTOSTART
Application
1529 001B04 .... DW ABORT
1530 001B06
1531 001B06 ;Z FACTORY -- set user area to delivery
condition
1532 001B06 ; UINIT U0 #INIT I->D SAVE init user
area
1533 001B06 ; ABORT ;
1534 001B06 HEADER FACTORY,7,'FACTORY',DOCOLON
1535 001B14 ............* DW UINIT,U0,NINIT,ITOD ; use kernel
user
area
1536 001B1C .... DW SAVE
1537 001B1E .... DW ABORT ; ABORT never returns
1538 001B20
1539 000000 PUBLIC FACTORYIP ; used to init IP register.
1540 001B20 FACTORYIP equ FACTORY+2
1541 001B20
1542 001B20 ;U WIPE -- erase flash but not kernel,
reset user area.
1543 001B20 HEADER WIPE,4,'WIPE',DOCOLON
1544 001B2A .... DW XISQUOTE
1545 001B2C 07 DB (wipmsg1-wipmsg0)
1546 001B2D 576970696E67 wipmsg0:DB 'Wiping'
1547 001B33 00 EVEN
1548 001B34 .... wipmsg1:DW ITYPE
1549 001B36 ....00C0....* DW lit,FLASHSTART,lit,FLASHEND-FLASHSTAR
T+1,FLERASE
1550 001B40 .... DW FACTORY ; EXIT
1551 001B42
1552 001B42 ;U MISC ========================================
================================
1553 001B42
1554 001B42 ;C 2CONSTANT -- define a Forth
double constant
1555 001B42 ; (machine code fragment)
1557 001B42 ; Note that the constant is stored in Code
space.
1558 001B42 HEADER TWOCONSTANT,9,'2CONSTANT',DOCOLON
1559 001B52 ............* DW BUILDS,ICOMMA,ICOMMA,XDOES
1560 000000 PUBLIC DOTWOCON
1561 001B5A DOTWOCON: ; ( -- w1 w2 )
1562 001B5A 2482 SUB #4,PSP ; make room on stack
1563 001B5C 84470200 MOV TOS,2(PSP)
1564 001B60 3746 MOV @W+,TOS ; fetch from parameter
field to TOS
1565 001B62 A4460000 MOV @W,0(PSP) ; fetch secon word from
parameter field to
NOS
1566 001B66 NEXT
1567 001B6A
1568 001B6A ;U \ -- backslash
1569 001B6A ; everything up to the end of the current line
is a comment.
1570 001B6A ; SOURCE >IN ! DROP ;
1571 001B6A IMMED BACKSLASH,1,'\\',DOCOLON
1572 001B72 ............* DW SOURCE,TOIN,STORE,DROP,EXIT
1573 001B7C
1574 001B7C ;Z .VER -- type message
1575 001B7C HEADER DOTVER,4,'.VER',DOCOLON
1576 001B86 ............* DW lit,version,COUNT,ITYPE
1577 001B8E ............ DW BASE,FETCH,BIN
1578 001B94 ............ DW COR,FETCH,DOT
1579 001B9A ........ DW BASE,STORE
1580 001B9E .... DW EXIT ; print cause of reset
1581 001BA0
1582 001BA0 ;U BELL -- send $07 to
Terminal
1583 001BA0 HEADER BELL,4,'BELL',DOCOLON
1584 001BAA ....0700....* DW lit,7,EMIT,EXIT
1585 001BB2
1586 001BB2 ;U BIN -- set number base to
binary
1587 001BB2 HEADER BIN,3,'BIN',DOCOLON
1588 001BBC ....0200....* DW lit,2,BASE,STORE,EXIT
1589 001BC6
1590 001BC6
1591 001BC6
1592 001BC6 ;U MCU specific words ==========================
================================
1593 001BC6
1594 001BC6 ;U 1MS -- wait about 1 millisecond
1595 001BC6 ; xx 0 DO yy 0 DO LOOP LOOP ; adjust xx and yy
to get a msec.
1596 001BC6 HEADER ONEMS,3,'1MS',DOCOLON
1597 001BD0 ....2900....* DW lit,41,lit,0,xdo
1598 001BDA ....0B00....*onems1: DW lit,11,lit,0,xdo
1599 001BE4 .... onems2: DW xloop
1600 001BE6 DEST onems2
1601 001BE8 .... DW xloop
1602 001BEA DEST onems1
1603 001BEC .... DW EXIT
1604 001BEE
1605 001BEE ;U MS n -- wait about n
milliseconds
1606 001BEE ; 0 DO 1MS LOOP ;
1607 001BEE HEADER MS,2,'MS',DOCOLON
1608 001BF6 ....0000.... DW lit,0,xdo
1609 001BFC ........ ms1: DW ONEMS,xloop
1610 001C00 DEST ms1
1611 001C02 .... DW EXIT
1612 001C04
1613 001C04
1614 001C04
1615 001C04 ;U Bit manipulation words ----------------------
--------------------------------
1616 001C04 ;U based on http://www.forth.org/svfig/Len/bits.
htm
1617 001C04
1618 001C04 ;U SET mask addr -- set bit from mask in
addr (cell); use even adr!
1619 001C04 HEADER wset,3,'SET',DOCODE
1620 001C0E A7D40000 BIS @PSP,0(TOS)
1621 001C12 2453 ADD #2,PSP
1622 001C14 3744 MOV @PSP+,TOS
1623 001C16 NEXT
1624 001C1A
1625 001C1A ;U CSET mask addr -- set bit from mask
in addr
1626 001C1A HEADER cset,4,'CSET',DOCODE
1627 001C24 E7D40000 BIS.B @PSP,0(TOS)
1628 001C28 2453 ADD #2,PSP
1629 001C2A 3744 MOV @PSP+,TOS
1630 001C2C NEXT
1631 001C30
1632 001C30 ;U CLR mask addr -- reset bit from mask in
addr (cell); use even adr!
1633 001C30 HEADER wclr,3,'CLR',DOCODE
1634 001C3A A7C40000 BIC @PSP,0(TOS)
1635 001C3E 2453 ADD #2,PSP
1636 001C40 3744 MOV @PSP+,TOS
1637 001C42 NEXT
1638 001C46
1639 001C46 ;U CCLR mask addr -- reset bit from mask
in addr
1640 001C46 HEADER cclr,4,'CCLR',DOCODE
1641 001C50 E7C40000 BIC.B @PSP,0(TOS)
1642 001C54 2453 ADD #2,PSP
1643 001C56 3744 MOV @PSP+,TOS
1644 001C58 NEXT
1645 001C5C
1646 001C5C ;U CTOGGLE mask addr -- flip bit from
mask in addr
1647 001C5C HEADER ctoggle,7,'CTOGGLE',DOCODE
1648 001C6A E7E40000 XOR.B @PSP,0(TOS)
1649 001C6E 2453 ADD #2,PSP
1650 001C70 3744 MOV @PSP+,TOS
1651 001C72 NEXT
1652 001C76
1653 001C76 ;U CGET mask addr -- flag test bit from
mask in addr
1654 001C76 HEADER cget,4,'CGET',DOCODE
1655 001C80 E7B40000 BIT.B @PSP,0(TOS)
1656 001C84 0224 JZ cget1
1657 001C86 3743 MOV #-1,TOS
1658 001C88 013C JMP cget2
1659 001C8A 0743 cget1:MOV #0, TOS
1660 001C8C 2453 cget2:ADD #2,PSP
1661 001C8E NEXT
1662 001C92
1663 001C92 ;U Memory info ---------------------------------
--------------------------------
1664 001C92
1665 001C92 ;Z MEMBOT -- adr begining of flash
1666 001C92 HEADER MEMBOT,6,'MEMBOT',DOCON
1667 001C9E 00C0 DW FLASHSTART
1668 001CA0
1669 001CA0 ;Z MEMTOP -- adr end of flash
1670 001CA0 HEADER MEMTOP,6,'MEMTOP',DOCON
1671 001CAC FFDF DW FLASHEND
1672 001CAE
1673 001CAE ;U MEM -- u bytes left in flash
1674 001CAE HEADER MEM,3,'MEM',DOCOLON
1675 001CB8 ....FFDF....* DW lit,FLASHEND,IHERE,MINUS
1676 001CC0 .... DW EXIT
1677 001CC2
1678 001CC2 ;U UNUSED -- u bytes left in RAM
1679 001CC2 HEADER UNUSED,6,'UNUSED',DOCOLON
1680 001CCE ....0004....* DW lit,RAMEND,HERE,MINUS
1681 001CD6 .... DW EXIT
1682 001CD8
1683 001CD8 ;U MCU Peripherie ------------------------------
--------------------------------
1684 001CD8
1685 001CD8 ;Z P1 -- adr address of port1 output
register
1686 001CD8 HEADER P1,2,'P1',DOCON
1687 001CE0 2100 DW P1OUT
1688 001CE2
1689 001CE2 ;Z P2 -- adr address of port2 output
register
1690 001CE2 HEADER P2,2,'P2',DOCON
1691 001CEA 2900 DW P2OUT
1692 001CEC
1693 001CEC ;Z P3 -- adr address of port2 output
register
1694 001CEC HEADER P3,2,'P3',DOCON
1695 001CF4 1900 DW P3OUT
1696 001CF6
1697 001CF6 ; Note: the first character sent from the MSP430
seems to get
1698 001CF6 ; scrambled. I conjecture this is because the
baud rate generator
1699 001CF6 ; has not reset to the new rate when we attempt
to send a character.
1700 001CF6 ; See init430f1611.s43 for delay after
initialization.
916 001CF6 #include "LaunchPad.s43"
1 001CF6 ; ----------------------------------------------
------------------------
2 001CF6 ; CF430G2553 is a Forth based on CamelForth
3 001CF6 ; for the Texas Instruments MSP430
4 001CF6 ;
5 001CF6 ; This program is free software; you can
redistribute it and/or modify
6 001CF6 ; it under the terms of the GNU General Public
License as published by
7 001CF6 ; the Free Software Foundation; either version 3
of the License, or
8 001CF6 ; (at your option) any later version.
9 001CF6 ;
10 001CF6 ; This program is distributed in the hope that
it will be useful,
11 001CF6 ; but WITHOUT ANY WARRANTY; without even the
implied warranty of
12 001CF6 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the
13 001CF6 ; GNU General Public License for more details.
14 001CF6 ;
15 001CF6 ; You should have received a copy of the GNU
General Public License
16 001CF6 ; along with this program. If not, see
.
17 001CF6 ;
18 001CF6 ; See LICENSE TERMS in Brads file readme.txt as
well.
19 001CF6
20 001CF6 ; ----------------------------------------------
------------------------
21 001CF6 ; LaunchPad.s43 - LaunchPad Suporting Words -
MSP430G2553
22 001CF6 ; ----------------------------------------------
------------------------
23 001CF6
24 001CF6
25 001CF6 ;U PORTS ---------------------------------------
------------------------
26 001CF6
27 001CF6 ; TI document SLAU144I - December 2004 - Revised
January 2012
28 001CF6 ; The digital I/O registers are listed in Table
8-2.
29 001CF6
30 001CF6 ;U \ P1in = $20
31 001CF6 ;U \ P1out = $21
32 001CF6 ;U \ P1dir = $22
33 001CF6
34 001CF6 ;U \ P2in = $28
35 001CF6 ;U \ P2out = $29
36 001CF6 ;U \ P2dir = $2A
37 001CF6
38 001CF6 ;U \ LED - portpinX->---resistor---LED---GND
39 001CF6 ;U \ P1.0 - red LED
40 001CF6 ;U \ P1.6 - green LED
41 001CF6
42 001CF6 ;U RED -- mask port red LED mask
and port address
43 001CF6 HEADER red,3,'RED',DOTWOCON
44 001D00 2100 DW P1OUT
45 001D02 0100 DW 00000001b
46 001D04
47 001D04 ;U GREEN -- mask port green LED mask
and port address
48 001D04 HEADER green,5,'GREEN',DOTWOCON
49 001D10 2100 DW P1OUT
50 001D12 4000 DW 01000000b
51 001D14
52 001D14 ;U \ Switch S2
53 001D14 ;U portpin P1.3 --->0_0----GND
54 001D14 ;U S2 -- mask port second button
mask and port address
55 001D14 HEADER S2,2,'S2',DOTWOCON
56 001D1C 2000 DW P1IN
57 001D1E 0800 DW 00001000b
58 001D20
59 001D20 ;U S2? -- f test button S2, true is
pressed
60 001D20 HEADER SQEST,3,'S2?',DOCOLON
61 001D2A ............* DW S2, cget, ZEROEQUAL, EXIT
62 001D32
63 001D32 ; ----------------------------------------------
------------------------
917 001D32
918 001D32
919 001D32 /*
920 001D32 ; DEBUG FORTH EXECUTION
921 001D32 ; debug serieal
922 001D32 PUBLIC DEBUGIP
923 001D32 DEBUGIP:
924 001D32 ; DW DOTID
925 001D32 DEBUG1:
926 001D32 ; DW TASK
927 001D32 DW KEY ; 1@A0 test 1=rot,@=grün,A=beide,0=a
us
928 001D32 DW DUP ;,DOTS,CR
929 001D32 DW STORELEDS
930 001D32 ; DW COLD
931 001D32 DW EMIT
932 001D32 DW lit,0,qbran
933 001D32 DW DEBUG1-$
934 001D32 DW bran,-2
935 001D32
936 001D32 /*
937 001D32 ; debugging only
938 001D32 HEADLESS CREATE,DOCOLON
939 001D32 HEADLESS ALLOT,DOCOLON
940 001D32 HEADLESS BUILDS,DOCOLON
941 001D32 HEADLESS ICOMMA,DOCOLON
942 001D32 HEADLESS XDOES,DOCOLON
943 001D32 HEADLESS IHERE,DOCOLON
944 001D32 HEADLESS IALLOT,DOCOLON
945 001D32 HEADLESS CELL,DOCOLON
946 001D32 HEADLESS PJOUT,DOCOLON
947 001D32 */
948 001D32
949 001D32
950 000000 PUBLIC lastword
951 001D32 lastword equ link
952 001D32
953 001D32 ; for debug map only:
954 001D32 CF430FRend:
955 001D32 #define CFlength = CF430FRend-CF430FRstart
956 001D32
957 001D32 END
ACCVIE #define, value: (0x20), line: 132:2
ACCVIFG #define, value: (0x0004u), line: 448:2
ADC10AE0_ #define, value: (0x004Au), line: 167:2 168:2
ADC10B1 #define, value: (0x002), line: 271:2
ADC10BUSY #define, value: (0x0001u), line: 211:2
ADC10CT #define, value: (0x004), line: 272:2
ADC10CTL0_ #define, value: (0x01B0u), line: 170:2 171:2
ADC10CTL1_ #define, value: (0x01B2u), line: 172:2 173:2
ADC10DF #define, value: (0x0200u), line: 220:2
ADC10DISABLE #define, value: (0x000), line: 274:2
ADC10DIV0 #define, value: (0x0020u), line: 216:2
ADC10DIV1 #define, value: (0x0040u), line: 217:2
ADC10DIV2 #define, value: (0x0080u), line: 218:2
ADC10DIV_0 #define, value: (0*0x20u), line: 238:2
ADC10DIV_1 #define, value: (1*0x20u), line: 239:2
ADC10DIV_2 #define, value: (2*0x20u), line: 240:2
ADC10DIV_3 #define, value: (3*0x20u), line: 241:2
ADC10DIV_4 #define, value: (4*0x20u), line: 242:2
ADC10DIV_5 #define, value: (5*0x20u), line: 243:2
ADC10DIV_6 #define, value: (6*0x20u), line: 244:2
ADC10DIV_7 #define, value: (7*0x20u), line: 245:2
ADC10DTC0_ #define, value: (0x0048u), line: 163:2 164:2
ADC10DTC1_ #define, value: (0x0049u), line: 165:2 166:2
ADC10FETCH #define, value: (0x001), line: 270:2
ADC10IE #define, value: (0x008), line: 183:2
ADC10IFG #define, value: (0x004), line: 182:2
ADC10MEM_ #define, value: (0x01B4u), line: 174:2 175:2
ADC10ON #define, value: (0x010), line: 184:2
ADC10SA_ #define, value: (0x01BCu), line: 176:2 177:2
ADC10SC #define, value: (0x001), line: 180:2
ADC10SHT0 #define, value: (0x800), line: 191:2
ADC10SHT1 #define, value: (0x1000u), line: 192:2
ADC10SHT_0 #define, value: (0*0x800u), line: 196:2
ADC10SHT_1 #define, value: (1*0x800u), line: 197:2
ADC10SHT_2 #define, value: (2*0x800u), line: 198:2
ADC10SHT_3 #define, value: (3*0x800u), line: 199:2
ADC10SR #define, value: (0x400), line: 190:2
ADC10SSEL0 #define, value: (0x0008u), line: 214:2
ADC10SSEL1 #define, value: (0x0010u), line: 215:2
ADC10SSEL_0 #define, value: (0*8u), line: 233:2
ADC10SSEL_1 #define, value: (1*8u), line: 234:2
ADC10SSEL_2 #define, value: (2*8u), line: 235:2
ADC10SSEL_3 #define, value: (3*8u), line: 236:2
ADC10TB #define, value: (0x008), line: 273:2
ADC10_VECTOR #define, value: (5 * 2u), line: 965:2
BCSCTL1_ #define, value: (0x0057u), line: 283:2 284:2
BCSCTL2_ #define, value: (0x0058u), line: 285:2 286:2
BCSCTL3_ #define, value: (0x0053u), line: 287:2 288:2
BIT0 #define, value: (0x0001u), line: 57:2
BIT1 #define, value: (0x0002u), line: 58:2
BIT2 #define, value: (0x0004u), line: 59:2
BIT3 #define, value: (0x0008u), line: 60:2
BIT4 #define, value: (0x0010u), line: 61:2
BIT5 #define, value: (0x0020u), line: 62:2
BIT6 #define, value: (0x0040u), line: 63:2
BIT7 #define, value: (0x0080u), line: 64:2
BIT8 #define, value: (0x0100u), line: 65:2
BIT9 #define, value: (0x0200u), line: 66:2
BITA #define, value: (0x0400u), line: 67:2
BITB #define, value: (0x0800u), line: 68:2
BITC #define, value: (0x1000u), line: 69:2
BITD #define, value: (0x2000u), line: 70:2
BITE #define, value: (0x4000u), line: 71:2
BITF #define, value: (0x8000u), line: 72:2
BLKWRT #define, value: (0x0080u), line: 423:2
BUSY #define, value: (0x0001u), line: 446:2
C #define, value: (0x0001u), line: 78:2
CACTL1_ #define, value: (0x0059u), line: 365:2 366:2
CACTL2_ #define, value: (0x005Au), line: 367:2 368:2
CAEX #define, value: (0x80), line: 379:2
CAF #define, value: (0x02), line: 387:2
CAIE #define, value: (0x02), line: 373:2
CAIES #define, value: (0x04), line: 374:2
CAIFG #define, value: (0x01), line: 372:2
CALBC1_12MHZ_ #define, value: (0x10FBu), line: 946:2 947:2
CALBC1_16MHZ_ #define, value: (0x10F9u), line: 942:2 943:2
CALBC1_1MHZ_ #define, value: (0x10FFu), line: 954:2 955:2
CALBC1_8MHZ_ #define, value: (0x10FDu), line: 950:2 951:2
CALDCO_12MHZ_ #define, value: (0x10FAu), line: 944:2 945:2
CALDCO_16MHZ_ #define, value: (0x10F8u), line: 940:2 941:2
CALDCO_1MHZ_ #define, value: (0x10FEu), line: 952:2 953:2
CALDCO_8MHZ_ #define, value: (0x10FCu), line: 948:2 949:2
CAON #define, value: (0x08), line: 375:2
CAOUT #define, value: (0x01), line: 386:2
CAP #define, value: (0x0100u), line: 604:2
CAPD0 #define, value: (0x01), line: 395:2
CAPD1 #define, value: (0x02), line: 396:2
CAPD2 #define, value: (0x04), line: 397:2
CAPD3 #define, value: (0x08), line: 398:2
CAPD4 #define, value: (0x10), line: 399:2
CAPD5 #define, value: (0x20), line: 400:2
CAPD6 #define, value: (0x40), line: 401:2
CAPD7 #define, value: (0x80), line: 402:2
CAPD_ #define, value: (0x005Bu), line: 369:2 370:2
CAREF0 #define, value: (0x10), line: 376:2
CAREF1 #define, value: (0x20), line: 377:2
CAREF_0 #define, value: (0x00), line: 381:2
CAREF_1 #define, value: (0x10), line: 382:2
CAREF_2 #define, value: (0x20), line: 383:2
CAREF_3 #define, value: (0x30), line: 384:2
CARSEL #define, value: (0x40), line: 378:2
CASHORT #define, value: (0x80), line: 393:2
CCI #define, value: (0x0008u), line: 609:2
CCIE #define, value: (0x0010u), line: 608:2
CCIFG #define, value: (0x0001u), line: 612:2
CCIS0 #define, value: (0x1000u), line: 601:2
CCIS1 #define, value: (0x2000u), line: 600:2
CCIS_0 #define, value: (0*0x1000u), line: 622:2
CCIS_1 #define, value: (1*0x1000u), line: 623:2
CCIS_2 #define, value: (2*0x1000u), line: 624:2
CCIS_3 #define, value: (3*0x1000u), line: 625:2
CCR0 #define, value: TACCR0, line: 565:2
CCR0_ #define, value: TACCR0_, line: 571:2
CCR1 #define, value: TACCR1, line: 566:2
CCR1_ #define, value: TACCR1_, line: 572:2
CCR2 #define, value: TACCR2, line: 567:2
CCR2_ #define, value: TACCR2_, line: 573:2
CCTL0 #define, value: TACCTL0, line: 562:2
CCTL0_ #define, value: TACCTL0_, line: 568:2
CCTL1 #define, value: TACCTL1, line: 563:2
CCTL1_ #define, value: TACCTL1_, line: 569:2
CCTL2 #define, value: TACCTL2, line: 564:2
CCTL2_ #define, value: TACCTL2_, line: 570:2
CFlength #define, value: = CF430FRend-CF430FRstart, line: 955
CM0 #define, value: (0x4000u), line: 599:2
CM1 #define, value: (0x8000u), line: 598:2
CM_0 #define, value: (0*0x4000u), line: 626:2
CM_1 #define, value: (1*0x4000u), line: 627:2
CM_2 #define, value: (2*0x4000u), line: 628:2
CM_3 #define, value: (3*0x4000u), line: 629:2
COMPARATORA_VECTOR #define, value: (11 * 2u), line: 971:2
CONSEQ0 #define, value: (0x0002u), line: 212:2
CONSEQ1 #define, value: (0x0004u), line: 213:2
CONSEQ_0 #define, value: (0*2u), line: 228:2
CONSEQ_1 #define, value: (1*2u), line: 229:2
CONSEQ_2 #define, value: (2*2u), line: 230:2
CONSEQ_3 #define, value: (3*2u), line: 231:2
COV #define, value: (0x0002u), line: 611:2
CPUOFF #define, value: (0x0010u), line: 83:2
DCO0 #define, value: (0x20), line: 295:2
DCO1 #define, value: (0x40), line: 296:2
DCO2 #define, value: (0x80), line: 297:2
DCOCTL_ #define, value: (0x0056u), line: 281:2 282:2
DEFC #define, line: 42:2 128:2 135:2 143:2 151:2
164:2 166:2 168:2 282:2
284:2 286:2 288:2 366:2
368:2 370:2 462:2 464:2
466:2 468:2 470:2 472:2
474:2 476:2 478:2 481:2
483:2 485:2 487:2 489:2
491:2 493:2 495:2 497:2
505:2 507:2 509:2 511:2
513:2 515:2 677:2 679:2
681:2 683:2 685:2 687:2
689:2 691:2 693:2 695:2
697:2 702:2 704:2 706:2
708:2 710:2 712:2 714:2
716:2 941:2 943:2 945:2
947:2 949:2 951:2 953:2
955:2
DEFW #define, line: 43:2 171:2 173:2 175:2 177:2
410:2 412:2 414:2 523:2
525:2 527:2 529:2 531:2
533:2 535:2 537:2 539:2
645:2 647:2 649:2 651:2
653:2 655:2 657:2 659:2
661:2 718:2 720:2 893:2
DIVA0 #define, value: (0x10), line: 303:2
DIVA1 #define, value: (0x20), line: 304:2
DIVA_0 #define, value: (0x00), line: 308:2
DIVA_1 #define, value: (0x10), line: 309:2
DIVA_2 #define, value: (0x20), line: 310:2
DIVA_3 #define, value: (0x30), line: 311:2
DIVM0 #define, value: (0x10), line: 316:2
DIVM1 #define, value: (0x20), line: 317:2
DIVM_0 #define, value: (0x00), line: 326:2
DIVM_1 #define, value: (0x10), line: 327:2
DIVM_2 #define, value: (0x20), line: 328:2
DIVM_3 #define, value: (0x30), line: 329:2
DIVS0 #define, value: (0x02), line: 313:2
DIVS1 #define, value: (0x04), line: 314:2
DIVS_0 #define, value: (0x00), line: 321:2
DIVS_1 #define, value: (0x02), line: 322:2
DIVS_2 #define, value: (0x04), line: 323:2
DIVS_3 #define, value: (0x06), line: 324:2
EMEX #define, value: (0x0020u), line: 451:2
ENC #define, value: (0x002), line: 181:2
ERASE #define, value: (0x0002u), line: 420:2 324
FAIL #define, value: (0x0080u), line: 453:2
FCTL1_ #define, value: (0x0128u), line: 409:2 410:2
FCTL2_ #define, value: (0x012Au), line: 411:2 412:2
FCTL3_ #define, value: (0x012Cu), line: 413:2 414:2
FLASHEND #define, value: (0xDFFF), line: 32:3 310 333 354 386
1549:5 1671:5 1675:5
FLASHSTART #define, value: (0xC000), line: 31:3 308 331 352 384
153:5 1453:5 1462:5 1497:5
1549:5 1549:5 1667:5
FN0 #define, value: (0x0001u), line: 426:2
FN1 #define, value: (0x0002u), line: 427:2
FN2 #define, value: (0x0004u), line: 429:2
FN3 #define, value: (0x0008u), line: 432:2
FN4 #define, value: (0x0010u), line: 435:2
FN5 #define, value: (0x0020u), line: 437:2
FRKEY #define, value: (0x9600u), line: 416:2
FSSEL0 #define, value: (0x0040u), line: 438:2
FSSEL1 #define, value: (0x0080u), line: 439:2
FSSEL_0 #define, value: (0x0000u), line: 441:2
FSSEL_1 #define, value: (0x0040u), line: 442:2
FSSEL_2 #define, value: (0x0080u), line: 443:2
FSSEL_3 #define, value: (0x00C0u), line: 444:2
FWKEY #define, value: (0xA500u), line: 417:2 323 324 326 327
367 368 371 372
399 400 403 404
427 428 446 447
FXKEY #define, value: (0x3300u), line: 418:2
GIE #define, value: (0x0008u), line: 82:2
HALLOT #define, value: IALLOT, line: 685:5 1048:5
HCCOMMA #define, value: ICCOMMA, line: 687:5 1046:5
HCFETCH #define, value: ICFETCH, line: 688:5 750:5 1048:5
HCOMMA #define, value: ICOMMA, line: 686:5 1045:5
HCOUNT #define, value: ICOUNT, line: 539:5 744:5 1360:5
HCSTORE #define, value: ICSTORE, line: 690:5 1117:5
HFETCH #define, value: IFETCH, line: 689:5 773:5 1107:5 1361:5
HHERE #define, value: IHERE, line: 684:5 1047:5
HSTORE #define, value: ISTORE, line: 691:5
HTYPE #define, value: ITYPE, line: 540:5 1360:5
HWORD #define, value: IWORDC, line: 541:5 1048:5
ID0 #define, value: (0x0040u), line: 578:2
ID1 #define, value: (0x0080u), line: 577:2
ID_0 #define, value: (0*0x40u), line: 589:2
ID_1 #define, value: (1*0x40u), line: 590:2
ID_2 #define, value: (2*0x40u), line: 591:2
ID_3 #define, value: (3*0x40u), line: 592:2
IE1_ #define, value: (0x0000u), line: 127:2 128:2
IE2_ #define, value: (0x0001u), line: 142:2 143:2
IFG1_ #define, value: (0x0002u), line: 134:2 135:2
IFG2_ #define, value: (0x0003u), line: 150:2 151:2
INCH0 #define, value: (0x1000u), line: 223:2
INCH1 #define, value: (0x2000u), line: 224:2
INCH2 #define, value: (0x4000u), line: 225:2
INCH3 #define, value: (0x8000u), line: 226:2
INCH_0 #define, value: (0*0x1000u), line: 252:2
INCH_1 #define, value: (1*0x1000u), line: 253:2
INCH_10 #define, value: (10*0x1000u), line: 262:2
INCH_11 #define, value: (11*0x1000u), line: 263:2
INCH_12 #define, value: (12*0x1000u), line: 264:2
INCH_13 #define, value: (13*0x1000u), line: 265:2
INCH_14 #define, value: (14*0x1000u), line: 266:2
INCH_15 #define, value: (15*0x1000u), line: 267:2
INCH_2 #define, value: (2*0x1000u), line: 254:2
INCH_3 #define, value: (3*0x1000u), line: 255:2
INCH_4 #define, value: (4*0x1000u), line: 256:2
INCH_5 #define, value: (5*0x1000u), line: 257:2
INCH_6 #define, value: (6*0x1000u), line: 258:2
INCH_7 #define, value: (7*0x1000u), line: 259:2
INCH_8 #define, value: (8*0x1000u), line: 260:2
INCH_9 #define, value: (9*0x1000u), line: 261:2
INDEX #define, value: R8, line: 46:3 635 638 639 649
653 662 667 676
691
INFOEND #define, value: (0x10FF), line: 28:3 315 359 391
INFOSEG #define, value: (128), line: 34:3 335 336
INFOSTART #define, value: (0x1000), line: 27:3 313 357 389
IP #define, value: R5, line: 41:3 63 64 68 69
78 79 80 108
118 130 158 159
160 161 178 184
189 196 204 212
217 223 230 237
244 250 257 263
275 281 286 293
339 375 452 460
466 473 480 485
490 495 500 506
511 516 521 526
531 542 554 563
570 578 590 613
613 614 621 622
641 652 655 666
669 678 687 693
701 702 730 761
777 794 811 835
851 871 889 900
1428:5 1566:5 1623:5 1630:5
1637:5 1644:5 1651:5 1661:5
IRACL #define, value: R12, line: 59:3 712 720 728 741
746 760
IRACM #define, value: R13, line: 60:3 713 721 729
IRBT #define, value: W, line: 61:3 717 718 725 742
748
IROP1 #define, value: TOS, line: 56:3 718 743 745 753
IROP2L #define, value: R10, line: 57:3 709 720 722 736
750
IROP2M #define, value: R11, line: 58:3 716 721 723 735
743 745 751 753
759
ISSH #define, value: (0x0100u), line: 219:2
KEYV #define, value: (0x0002u), line: 447:2
LFXT1OF #define, value: (0x01), line: 336:2
LFXT1S0 #define, value: (0x10), line: 340:2
LFXT1S1 #define, value: (0x20), line: 341:2
LFXT1S_0 #define, value: (0x00), line: 350:2
LFXT1S_1 #define, value: (0x10), line: 351:2
LFXT1S_2 #define, value: (0x20), line: 352:2
LFXT1S_3 #define, value: (0x30), line: 353:2
LIMIT #define, value: R9, line: 47:3 634 636 637 639
654 668 677 692
LOCK #define, value: (0x0010u), line: 450:2 327 372 404 447
LOCKA #define, value: (0x0040u), line: 452:2
LPM0 #define, value: (CPUOFF), line: 91:2
LPM1 #define, value: (SCG0+CPUOFF), line: 92:2
LPM2 #define, value: (SCG1+CPUOFF), line: 93:2
LPM3 #define, value: (SCG1+SCG0+CPUOFF), line: 94:2
LPM4 #define, value: (SCG1+SCG0+OSCOFF+CPUOFF), line: 95:2
MAINSEG #define, value: (512), line: 33:3 335
MC0 #define, value: (0x0010u), line: 580:2
MC1 #define, value: (0x0020u), line: 579:2
MC_0 #define, value: (0*0x10u), line: 585:2
MC_1 #define, value: (1*0x10u), line: 586:2
MC_2 #define, value: (2*0x10u), line: 587:2
MC_3 #define, value: (3*0x10u), line: 588:2
MERAS #define, value: (0x0004u), line: 421:2
MOD0 #define, value: (0x01), line: 290:2
MOD1 #define, value: (0x02), line: 291:2
MOD2 #define, value: (0x04), line: 292:2
MOD3 #define, value: (0x08), line: 293:2
MOD4 #define, value: (0x10), line: 294:2
MSC #define, value: (0x080), line: 187:2
N #define, value: (0x0004u), line: 80:2
NMIIE #define, value: (0x10), line: 131:2
NMIIFG #define, value: (0x10), line: 140:2
NMI_VECTOR #define, value: (14 * 2u), line: 974:2
OFIE #define, value: (0x02), line: 130:2
OFIFG #define, value: (0x02), line: 137:2
OSCOFF #define, value: (0x0020u), line: 84:2
OUT #define, value: (0x0004u), line: 610:2
OUTMOD0 #define, value: (0x0020u), line: 607:2
OUTMOD1 #define, value: (0x0040u), line: 606:2
OUTMOD2 #define, value: (0x0080u), line: 605:2
OUTMOD_0 #define, value: (0*0x20u), line: 614:2
OUTMOD_1 #define, value: (1*0x20u), line: 615:2
OUTMOD_2 #define, value: (2*0x20u), line: 616:2
OUTMOD_3 #define, value: (3*0x20u), line: 617:2
OUTMOD_4 #define, value: (4*0x20u), line: 618:2
OUTMOD_5 #define, value: (5*0x20u), line: 619:2
OUTMOD_6 #define, value: (6*0x20u), line: 620:2
OUTMOD_7 #define, value: (7*0x20u), line: 621:2
P1DIR_ #define, value: (0x0022u), line: 465:2 466:2
P1IES_ #define, value: (0x0024u), line: 469:2 470:2
P1IE_ #define, value: (0x0025u), line: 471:2 472:2
P1IFG_ #define, value: (0x0023u), line: 467:2 468:2
P1IN_ #define, value: (0x0020u), line: 461:2 462:2
P1OUT_ #define, value: (0x0021u), line: 463:2 464:2
P1REN_ #define, value: (0x0027u), line: 477:2 478:2
P1SEL2_ #define, value: (0x0041u), line: 475:2 476:2
P1SEL_ #define, value: (0x0026u), line: 473:2 474:2
P2CA0 #define, value: (0x04), line: 388:2
P2CA1 #define, value: (0x08), line: 389:2
P2CA2 #define, value: (0x10), line: 390:2
P2CA3 #define, value: (0x20), line: 391:2
P2CA4 #define, value: (0x40), line: 392:2
P2DIR_ #define, value: (0x002Au), line: 484:2 485:2
P2IES_ #define, value: (0x002Cu), line: 488:2 489:2
P2IE_ #define, value: (0x002Du), line: 490:2 491:2
P2IFG_ #define, value: (0x002Bu), line: 486:2 487:2
P2IN_ #define, value: (0x0028u), line: 480:2 481:2
P2OUT_ #define, value: (0x0029u), line: 482:2 483:2
P2REN_ #define, value: (0x002Fu), line: 496:2 497:2
P2SEL2_ #define, value: (0x0042u), line: 494:2 495:2
P2SEL_ #define, value: (0x002Eu), line: 492:2 493:2
P3DIR_ #define, value: (0x001Au), line: 508:2 509:2
P3IN_ #define, value: (0x0018u), line: 504:2 505:2
P3OUT_ #define, value: (0x0019u), line: 506:2 507:2
P3REN_ #define, value: (0x0010u), line: 514:2 515:2
P3SEL2_ #define, value: (0x0043u), line: 512:2 513:2
P3SEL_ #define, value: (0x001Bu), line: 510:2 511:2
PORIFG #define, value: (0x04), line: 138:2
PORT1_VECTOR #define, value: (2 * 2u), line: 963:2
PORT2_VECTOR #define, value: (3 * 2u), line: 964:2
PREFIXPROMPT #define, value: 0, line: 941:5 947:5 956:5
PSP #define, value: R4, line: 40:3 55 61 62 105
106 115 116 126
127 155 156 176
177 188 193 194
200 201 202 208
209 210 211 216
222 227 228 234
235 241 242 243
248 249 254 255
262 279 280 290
292 302 338 345
374 379 420 421
451 459 464 465
470 471 472 477
484 489 494 535
546 574 586 598
619 637 640 663
674 675 683 684
709 728 735 736
759 768 769 776
785 786 793 799
800 810 824 825
833 840 841 849
856 857 888 896
897 904 905 1421:5
1562:5 1563:5 1565:5 1620:5
1621:5 1622:5 1627:5 1628:5
1629:5 1634:5 1635:5 1636:5
1641:5 1642:5 1643:5 1648:5
1649:5 1650:5 1655:5 1660:5
Q #define, value: R12, line: 52:3 436 437 438
RAMEND #define, value: (0x0400), line: 30:3 1680:5
RAMSTART #define, value: (0x0200), line: 29:3
READ_ONLY #define, value: const, line: 50:2 462:2 481:2 505:2 523:2
645:2 689:2 714:2 941:2
943:2 945:2 947:2 949:2
951:2 953:2 955:2
REF2_5V #define, value: (0x040), line: 186:2
REFBURST #define, value: (0x100), line: 188:2
REFON #define, value: (0x020), line: 185:2
REFOUT #define, value: (0x200), line: 189:2
RESET_VECTOR #define, value: (15 * 2u), line: 975:2
RSEL0 #define, value: (0x01), line: 299:2
RSEL1 #define, value: (0x02), line: 300:2
RSEL2 #define, value: (0x04), line: 301:2
RSEL3 #define, value: (0x08), line: 302:2
RSP #define, value: SP, line: 39:3 68 229 236 256
261 633 634 635
653 654 667 668
685 686 691 692
698 700
RSTIFG #define, value: (0x08), line: 139:2
SCCI #define, value: (0x0400u), line: 603:2
SCG0 #define, value: (0x0040u), line: 85:2
SCG1 #define, value: (0x0080u), line: 86:2
SCS #define, value: (0x0800u), line: 602:2
SEGWRT #define, value: (0x0080u), line: 424:2
SELM0 #define, value: (0x40), line: 318:2
SELM1 #define, value: (0x80), line: 319:2
SELM_0 #define, value: (0x00), line: 331:2
SELM_1 #define, value: (0x40), line: 332:2
SELM_2 #define, value: (0x80), line: 333:2
SELM_3 #define, value: (0xC0), line: 334:2
SELS #define, value: (0x08), line: 315:2
SHS0 #define, value: (0x0400u), line: 221:2
SHS1 #define, value: (0x0800u), line: 222:2
SHS_0 #define, value: (0*0x400u), line: 247:2
SHS_1 #define, value: (1*0x400u), line: 248:2
SHS_2 #define, value: (2*0x400u), line: 249:2
SHS_3 #define, value: (3*0x400u), line: 250:2
SREF0 #define, value: (0x2000u), line: 193:2
SREF1 #define, value: (0x4000u), line: 194:2
SREF2 #define, value: (0x8000u), line: 195:2
SREF_0 #define, value: (0*0x2000u), line: 201:2
SREF_1 #define, value: (1*0x2000u), line: 202:2
SREF_2 #define, value: (2*0x2000u), line: 203:2
SREF_3 #define, value: (3*0x2000u), line: 204:2
SREF_4 #define, value: (4*0x2000u), line: 205:2
SREF_5 #define, value: (5*0x2000u), line: 206:2
SREF_6 #define, value: (6*0x2000u), line: 207:2
SREF_7 #define, value: (7*0x2000u), line: 208:2
T #define, value: R13, line: 53:3
TA0CCR0_ #define, value: (0x0172u), line: 534:2 535:2
TA0CCR1_ #define, value: (0x0174u), line: 536:2 537:2
TA0CCR2_ #define, value: (0x0176u), line: 538:2 539:2
TA0CCTL0_ #define, value: (0x0162u), line: 526:2 527:2
TA0CCTL1_ #define, value: (0x0164u), line: 528:2 529:2
TA0CCTL2_ #define, value: (0x0166u), line: 530:2 531:2
TA0CTL_ #define, value: (0x0160u), line: 524:2 525:2
TA0IV_ #define, value: (0x012Eu), line: 522:2 523:2
TA0IV_6 #define, value: (0x0006u), line: 635:2
TA0IV_8 #define, value: (0x0008u), line: 636:2
TA0IV_NONE #define, value: (0x0000u), line: 632:2
TA0IV_TACCR1 #define, value: (0x0002u), line: 633:2
TA0IV_TACCR2 #define, value: (0x0004u), line: 634:2
TA0IV_TAIFG #define, value: (0x000Au), line: 637:2
TA0R_ #define, value: (0x0170u), line: 532:2 533:2
TA1CCR0_ #define, value: (0x0192u), line: 656:2 657:2
TA1CCR1_ #define, value: (0x0194u), line: 658:2 659:2
TA1CCR2_ #define, value: (0x0196u), line: 660:2 661:2
TA1CCTL0_ #define, value: (0x0182u), line: 648:2 649:2
TA1CCTL1_ #define, value: (0x0184u), line: 650:2 651:2
TA1CCTL2_ #define, value: (0x0186u), line: 652:2 653:2
TA1CTL_ #define, value: (0x0180u), line: 646:2 647:2
TA1IV_ #define, value: (0x011Eu), line: 644:2 645:2
TA1IV_NONE #define, value: (0x0000u), line: 666:2
TA1IV_TACCR1 #define, value: (0x0002u), line: 667:2
TA1IV_TACCR2 #define, value: (0x0004u), line: 668:2
TA1IV_TAIFG #define, value: (0x000Au), line: 669:2
TA1R_ #define, value: (0x0190u), line: 654:2 655:2
TACCR0 #define, value: TA0CCR0, line: 548:2
TACCR0_ #define, value: TA0CCR0_, line: 557:2
TACCR1 #define, value: TA0CCR1, line: 549:2
TACCR1_ #define, value: TA0CCR1_, line: 558:2
TACCR2 #define, value: TA0CCR2, line: 550:2
TACCR2_ #define, value: TA0CCR2_, line: 559:2
TACCTL0 #define, value: TA0CCTL0, line: 544:2
TACCTL0_ #define, value: TA0CCTL0_, line: 553:2
TACCTL1 #define, value: TA0CCTL1, line: 545:2
TACCTL1_ #define, value: TA0CCTL1_, line: 554:2
TACCTL2 #define, value: TA0CCTL2, line: 546:2
TACCTL2_ #define, value: TA0CCTL2_, line: 555:2
TACLR #define, value: (0x0004u), line: 581:2
TACTL #define, value: TA0CTL, line: 543:2
TACTL_ #define, value: TA0CTL_, line: 552:2
TAIE #define, value: (0x0002u), line: 582:2
TAIFG #define, value: (0x0001u), line: 583:2
TAIV #define, value: TA0IV, line: 542:2
TAIV_ #define, value: TA0IV_, line: 551:2
TAR #define, value: TA0R, line: 547:2
TAR_ #define, value: TA0R_, line: 556:2
TASSEL0 #define, value: (0x0100u), line: 576:2
TASSEL1 #define, value: (0x0200u), line: 575:2
TASSEL_0 #define, value: (0*0x100u), line: 593:2
TASSEL_1 #define, value: (1*0x100u), line: 594:2
TASSEL_2 #define, value: (2*0x100u), line: 595:2
TASSEL_3 #define, value: (3*0x100u), line: 596:2
TIMER0_A0_VECTOR #define, value: (9 * 2u), line: 969:2
TIMER0_A1_VECTOR #define, value: (8 * 2u), line: 968:2
TIMER1_A0_VECTOR #define, value: (13 * 2u), line: 973:2
TIMER1_A1_VECTOR #define, value: (12 * 2u), line: 972:2
TOS #define, value: R7, line: 43:3 54 55 62 63
106 107 116 117
127 128 129 156
157 177 182 188
194 195 202 203
209 210 221 222
228 229 235 236
242 243 248 249
255 256 261 262
274 274 279 280
285 285 291 292
303 305 338 346
348 352 354 357
359 370 374 380
384 386 389 391
402 422 431 441
449 451 459 464
465 470 472 478
479 484 489 494
499 504 505 510
515 520 525 525
530 536 539 541
547 551 553 561
562 562 567 567
568 568 569 575
577 587 589 599
618 619 638 640
662 663 675 676
677 684 685 686
718 729 743 745
753 760 772 776
787 791 793 801
803 804 808 810
828 834 844 850
858 863 868 868
869 869 870 887
888 897 898 905
57:4 1419:5 1420:5 1421:5
1423:5 1425:5 1563:5 1564:5
1620:5 1622:5 1627:5 1629:5
1634:5 1636:5 1641:5 1643:5
1648:5 1650:5 1655:5 1657:5
1659:5
UC0IE #define, value: IE2, line: 144:2
UC0IFG #define, value: IFG2, line: 152:2
UC7BIT #define, value: (0x10), line: 726:2
UCA0ABCTL_ #define, value: (0x005Du), line: 692:2 693:2
UCA0BR0_ #define, value: (0x0062u), line: 680:2 681:2
UCA0BR1_ #define, value: (0x0063u), line: 682:2 683:2
UCA0CTL0_ #define, value: (0x0060u), line: 676:2 677:2
UCA0CTL1_ #define, value: (0x0061u), line: 678:2 679:2
UCA0IRRCTL_ #define, value: (0x005Fu), line: 696:2 697:2
UCA0IRTCTL_ #define, value: (0x005Eu), line: 694:2 695:2
UCA0MCTL_ #define, value: (0x0064u), line: 684:2 685:2
UCA0RXBUF_ #define, value: (0x0066u), line: 688:2 689:2
UCA0RXIE #define, value: (0x01), line: 145:2
UCA0RXIFG #define, value: (0x01), line: 153:2 894 906
UCA0STAT_ #define, value: (0x0065u), line: 686:2 687:2
UCA0TXBUF_ #define, value: (0x0067u), line: 690:2 691:2
UCA0TXIE #define, value: (0x02), line: 146:2
UCA0TXIFG #define, value: (0x02), line: 154:2 885
UCA10 #define, value: (0x80), line: 738:2
UCABDEN #define, value: (0x01), line: 862:2
UCADDR #define, value: (0x02), line: 816:2
UCALIE #define, value: (0x01), line: 827:2
UCALIFG #define, value: (0x01), line: 835:2
UCB0BR0_ #define, value: (0x006Au), line: 705:2 706:2
UCB0BR1_ #define, value: (0x006Bu), line: 707:2 708:2
UCB0CTL0_ #define, value: (0x0068u), line: 701:2 702:2
UCB0CTL1_ #define, value: (0x0069u), line: 703:2 704:2
UCB0I2CIE_ #define, value: (0x006Cu), line: 709:2 710:2
UCB0I2COA_ #define, value: (0x0118u), line: 717:2 718:2
UCB0I2CSA_ #define, value: (0x011Au), line: 719:2 720:2
UCB0RXBUF_ #define, value: (0x006Eu), line: 713:2 714:2
UCB0RXIE #define, value: (0x04), line: 147:2
UCB0RXIFG #define, value: (0x04), line: 155:2
UCB0STAT_ #define, value: (0x006Du), line: 711:2 712:2
UCB0TXBUF_ #define, value: (0x006Fu), line: 715:2 716:2
UCB0TXIE #define, value: (0x08), line: 148:2
UCB0TXIFG #define, value: (0x08), line: 156:2
UCBBUSY #define, value: (0x10), line: 831:2
UCBRF0 #define, value: (0x10), line: 778:2
UCBRF1 #define, value: (0x20), line: 777:2
UCBRF2 #define, value: (0x40), line: 776:2
UCBRF3 #define, value: (0x80), line: 775:2
UCBRF_0 #define, value: (0x00), line: 784:2
UCBRF_1 #define, value: (0x10), line: 785:2
UCBRF_10 #define, value: (0xA0), line: 794:2
UCBRF_11 #define, value: (0xB0), line: 795:2
UCBRF_12 #define, value: (0xC0), line: 796:2
UCBRF_13 #define, value: (0xD0), line: 797:2
UCBRF_14 #define, value: (0xE0), line: 798:2
UCBRF_15 #define, value: (0xF0), line: 799:2
UCBRF_2 #define, value: (0x20), line: 786:2
UCBRF_3 #define, value: (0x30), line: 787:2
UCBRF_4 #define, value: (0x40), line: 788:2
UCBRF_5 #define, value: (0x50), line: 789:2
UCBRF_6 #define, value: (0x60), line: 790:2
UCBRF_7 #define, value: (0x70), line: 791:2
UCBRF_8 #define, value: (0x80), line: 792:2
UCBRF_9 #define, value: (0x90), line: 793:2
UCBRK #define, value: (0x08), line: 814:2
UCBRKIE #define, value: (0x10), line: 751:2
UCBRS0 #define, value: (0x02), line: 781:2
UCBRS1 #define, value: (0x04), line: 780:2
UCBRS2 #define, value: (0x08), line: 779:2
UCBRS_0 #define, value: (0x00), line: 801:2
UCBRS_1 #define, value: (0x02), line: 802:2
UCBRS_2 #define, value: (0x04), line: 803:2
UCBRS_3 #define, value: (0x06), line: 804:2
UCBRS_4 #define, value: (0x08), line: 805:2
UCBRS_5 #define, value: (0x0A), line: 806:2
UCBRS_6 #define, value: (0x0C), line: 807:2
UCBRS_7 #define, value: (0x0E), line: 808:2
UCBTOE #define, value: (0x04), line: 860:2
UCBUSY #define, value: (0x01), line: 817:2
UCCKPH #define, value: (0x80), line: 733:2
UCCKPL #define, value: (0x40), line: 734:2
UCDELIM0 #define, value: (0x10), line: 858:2
UCDELIM1 #define, value: (0x20), line: 857:2
UCDORM #define, value: (0x08), line: 752:2
UCFE #define, value: (0x40), line: 811:2
UCGC #define, value: (0x20), line: 830:2
UCGCEN #define, value: (0x8000u), line: 864:2
UCIDLE #define, value: (0x02), line: 818:2
UCIREN #define, value: (0x01), line: 844:2
UCIRRXFE #define, value: (0x01), line: 853:2
UCIRRXFL0 #define, value: (0x04), line: 851:2
UCIRRXFL1 #define, value: (0x08), line: 850:2
UCIRRXFL2 #define, value: (0x10), line: 849:2
UCIRRXFL3 #define, value: (0x20), line: 848:2
UCIRRXFL4 #define, value: (0x40), line: 847:2
UCIRRXFL5 #define, value: (0x80), line: 846:2
UCIRRXPL #define, value: (0x02), line: 852:2
UCIRTXCLK #define, value: (0x02), line: 843:2
UCIRTXPL0 #define, value: (0x04), line: 842:2
UCIRTXPL1 #define, value: (0x08), line: 841:2
UCIRTXPL2 #define, value: (0x10), line: 840:2
UCIRTXPL3 #define, value: (0x20), line: 839:2
UCIRTXPL4 #define, value: (0x40), line: 838:2
UCIRTXPL5 #define, value: (0x80), line: 837:2
UCLISTEN #define, value: (0x80), line: 810:2
UCMM #define, value: (0x20), line: 740:2
UCMODE0 #define, value: (0x02), line: 729:2
UCMODE1 #define, value: (0x04), line: 728:2
UCMODE_0 #define, value: (0x00), line: 742:2
UCMODE_1 #define, value: (0x02), line: 743:2
UCMODE_2 #define, value: (0x04), line: 744:2
UCMODE_3 #define, value: (0x06), line: 745:2
UCMSB #define, value: (0x20), line: 725:2
UCMST #define, value: (0x08), line: 735:2
UCNACKIE #define, value: (0x08), line: 824:2
UCNACKIFG #define, value: (0x08), line: 832:2
UCOA0 #define, value: (0x0001u), line: 874:2
UCOA1 #define, value: (0x0002u), line: 873:2
UCOA2 #define, value: (0x0004u), line: 872:2
UCOA3 #define, value: (0x0008u), line: 871:2
UCOA4 #define, value: (0x0010u), line: 870:2
UCOA5 #define, value: (0x0020u), line: 869:2
UCOA6 #define, value: (0x0040u), line: 868:2
UCOA7 #define, value: (0x0080u), line: 867:2
UCOA8 #define, value: (0x0100u), line: 866:2
UCOA9 #define, value: (0x0200u), line: 865:2
UCOE #define, value: (0x20), line: 812:2
UCOS16 #define, value: (0x01), line: 782:2
UCPAR #define, value: (0x40), line: 724:2
UCPE #define, value: (0x10), line: 813:2
UCPEN #define, value: (0x80), line: 723:2
UCRXEIE #define, value: (0x20), line: 750:2
UCRXERR #define, value: (0x04), line: 815:2
UCSA0 #define, value: (0x0001u), line: 885:2
UCSA1 #define, value: (0x0002u), line: 884:2
UCSA2 #define, value: (0x0004u), line: 883:2
UCSA3 #define, value: (0x0008u), line: 882:2
UCSA4 #define, value: (0x0010u), line: 881:2
UCSA5 #define, value: (0x0020u), line: 880:2
UCSA6 #define, value: (0x0040u), line: 879:2
UCSA7 #define, value: (0x0080u), line: 878:2
UCSA8 #define, value: (0x0100u), line: 877:2
UCSA9 #define, value: (0x0200u), line: 876:2
UCSCLLOW #define, value: (0x40), line: 829:2
UCSLA10 #define, value: (0x40), line: 739:2
UCSPB #define, value: (0x08), line: 727:2
UCSSEL0 #define, value: (0x40), line: 749:2
UCSSEL1 #define, value: (0x80), line: 748:2
UCSSEL_0 #define, value: (0x00), line: 770:2
UCSSEL_1 #define, value: (0x40), line: 771:2
UCSSEL_2 #define, value: (0x80), line: 772:2
UCSSEL_3 #define, value: (0xC0), line: 773:2
UCSTOE #define, value: (0x08), line: 859:2
UCSTPIE #define, value: (0x04), line: 825:2
UCSTPIFG #define, value: (0x04), line: 833:2
UCSTTIE #define, value: (0x02), line: 826:2
UCSTTIFG #define, value: (0x02), line: 834:2
UCSWRST #define, value: (0x01), line: 755:2
UCSYNC #define, value: (0x01), line: 730:2
UCTR #define, value: (0x10), line: 766:2
UCTXADDR #define, value: (0x04), line: 753:2
UCTXBRK #define, value: (0x02), line: 754:2
UCTXNACK #define, value: (0x08), line: 767:2
UCTXSTP #define, value: (0x04), line: 768:2
UCTXSTT #define, value: (0x02), line: 769:2
USCIAB0RX_VECTOR #define, value: (7 * 2u), line: 967:2
USCIAB0TX_VECTOR #define, value: (6 * 2u), line: 966:2
V #define, value: (0x0100u), line: 81:2
W #define, value: R6, line: 42:3 54 56 64 64
69 69 79 80
80 107 108 108
117 118 118 128
130 130 138 138
139 157 159 161
161 178 178 184
184 189 189 193
195 196 196 200
203 204 204 208
211 212 212 217
217 223 223 230
230 237 237 244
244 250 250 257
257 263 263 275
275 281 281 286
286 290 291 293
293 302 303 305
308 310 313 315
325 331 333 335
336 339 339 345
348 370 375 375
379 380 402 420
433 439 440 443
444 452 452 460
460 466 466 473
473 477 478 479
480 480 485 485
490 490 495 495
500 500 506 506
511 511 516 516
521 521 526 526
531 531 535 538
538 541 542 542
546 550 553 554
554 563 563 570
570 574 575 578
578 586 587 590
590 598 599 614
614 622 622 641
641 655 655 669
669 678 678 687
687 693 693 702
702 717 718 725
730 730 742 748
761 761 769 772
773 777 777 785
789 790 794 794
799 803 806 807
811 811 825 828
830 833 835 835
841 844 846 849
851 851 856 860
871 871 889 889
900 900 1422:5 1426:5
1428:5 1428:5 1564:5 1565:5
1566:5 1566:5 1623:5 1623:5
1630:5 1630:5 1637:5 1637:5
1644:5 1644:5 1651:5 1651:5
1661:5 1661:5
WAIT #define, value: (0x0008u), line: 449:2
WDTCNTCL #define, value: (0x0008u), line: 898:2
WDTCTL_ #define, value: (0x0120u), line: 892:2 893:2
WDTHOLD #define, value: (0x0080u), line: 902:2
WDTIE #define, value: (0x01), line: 129:2
WDTIFG #define, value: (0x01), line: 136:2
WDTIS0 #define, value: (0x0001u), line: 895:2
WDTIS1 #define, value: (0x0002u), line: 896:2
WDTNMI #define, value: (0x0020u), line: 900:2
WDTNMIES #define, value: (0x0040u), line: 901:2
WDTPW #define, value: (0x5A00u), line: 904:2
WDTSSEL #define, value: (0x0004u), line: 897:2
WDTTMSEL #define, value: (0x0010u), line: 899:2
WDT_ADLY_1000 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL), line: 913:2
WDT_ADLY_16 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1), line: 915:2
WDT_ADLY_1_9 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0), line: 916:2
WDT_ADLY_250 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0), line: 914:2
WDT_ARST_1000 #define, value: (WDTPW+WDTCNTCL+WDTSSEL), line: 924:2
WDT_ARST_16 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1), line: 926:2
WDT_ARST_1_9 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0), line: 927:2
WDT_ARST_250 #define, value: (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0), line: 925:2
WDT_MDLY_0_064 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0), line: 911:2
WDT_MDLY_0_5 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1), line: 910:2
WDT_MDLY_32 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL), line: 908:2
WDT_MDLY_8 #define, value: (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0), line: 909:2
WDT_MRST_0_064 #define, value: (WDTPW+WDTCNTCL+WDTIS1+WDTIS0), line: 922:2
WDT_MRST_0_5 #define, value: (WDTPW+WDTCNTCL+WDTIS1), line: 921:2
WDT_MRST_32 #define, value: (WDTPW+WDTCNTCL), line: 919:2
WDT_MRST_8 #define, value: (WDTPW+WDTCNTCL+WDTIS0), line: 920:2
WDT_VECTOR #define, value: (10 * 2u), line: 970:2
WRT #define, value: (0x0040u), line: 422:2 368 400 428
X #define, value: R10, line: 50:3 421 435 436 443
768 770 774 786
789 800 804 805
807 824 826 831
834 840 842 847
850 857 860 862
XCAP0 #define, value: (0x04), line: 338:2
XCAP1 #define, value: (0x08), line: 339:2
XCAP_0 #define, value: (0x00), line: 345:2
XCAP_1 #define, value: (0x04), line: 346:2
XCAP_2 #define, value: (0x08), line: 347:2
XCAP_3 #define, value: (0x0C), line: 348:2
XT2OF #define, value: (0x02), line: 337:2
XT2OFF #define, value: (0x80), line: 306:2
XT2S0 #define, value: (0x40), line: 342:2
XT2S1 #define, value: (0x80), line: 343:2
XT2S_0 #define, value: (0x00), line: 355:2
XT2S_1 #define, value: (0x40), line: 356:2
XT2S_2 #define, value: (0x80), line: 357:2
XT2S_3 #define, value: (0xC0), line: 358:2
XTS #define, value: (0x40), line: 305:2
Y #define, value: R11, line: 51:3 435 438 439
Z #define, value: (0x0002u), line: 79:2
__430X_CORE__ #define, value: 1, line: 0
__430_CORE__ #define, value: 0, line: 0
__A430__ #define, value: 1, line: 0
__BUILD_NUMBER__ #define, line: 0
__CORE__ #define, value: 0, line: 0
__DATE__ #define, line: 0 41
__FILE__ #define, line: 0
__IAR_SYSTEMS_ASM #define, line: 0
__IAR_SYSTEMS_ASM__ #define, line: 0
__LINE__ #define, line: 0
__MSP430G2553 #define, value: , line: 16:2
__MSP430G2553__ #define, value: 1, line: 0
__MSP430_HAS_ADC10__ #define, value: , line: 161:2
__MSP430_HAS_BC2__ #define, value: , line: 279:2
__MSP430_HAS_CAPLUS__ #define, value: , line: 363:2
__MSP430_HAS_FLASH2__ #define, value: , line: 407:2
__MSP430_HAS_PORT1_R__ #define, value: , line: 458:2
__MSP430_HAS_PORT2_R__ #define, value: , line: 459:2
__MSP430_HAS_PORT3_R__ #define, value: , line: 502:2
__MSP430_HAS_T1A3__ #define, value: , line: 642:2
__MSP430_HAS_TA3__ #define, value: , line: 520:2
__MSP430_HAS_USCI__ #define, value: , line: 674:2
__MSP430_HAS_WDT__ #define, value: , line: 890:2
__SUBVERSION__ #define, line: 0
__TID__ #define, line: 0 24:2
__TIME__ #define, line: 0
__VER__ #define, line: 0
__msp430 #define, value: , line: 9:1
Segment Type Mode
----------------------------------------
CODE UNTYPED REL
Label Mode Type Segment Value/Offset
------------------------------------------------------------------------------
ABBS REL CONST PUB UNTYP. CODE ACA
ABORT REL CONST PUB UNTYP. CODE 1430
ABORTQUOTE REL CONST PUB UNTYP. CODE 145C
ACC1 REL CONST UNTYP. CODE D48
ACC3 REL CONST UNTYP. CODE D7E
ACC4 REL CONST UNTYP. CODE D88
ACC5 REL CONST UNTYP. CODE D8C
ACCEPT REL CONST PUB UNTYP. CODE D3E
ADC10AE0 ABS CONST UNTYP. ASEG 4A
ADC10CTL0 ABS CONST UNTYP. ASEG 1B0
ADC10CTL1 ABS CONST UNTYP. ASEG 1B2
ADC10DTC0 ABS CONST UNTYP. ASEG 48
ADC10DTC1 ABS CONST UNTYP. ASEG 49
ADC10MEM ABS CONST UNTYP. ASEG 1B4
ADC10SA ABS CONST UNTYP. ASEG 1BC
AGAIN REL CONST PUB UNTYP. CODE 16C2
ALIGNED REL CONST PUB UNTYP. CODE 81A
ALIGNN REL CONST PUB UNTYP. CODE 800
ALLOT REL CONST PUB UNTYP. CODE 102C
ANDD REL CONST PUB UNTYP. CODE 40C
APP REL CONST PUB UNTYP. CODE 9D8
APPCRC REL CONST PUB UNTYP. CODE 1A3E
APPU0 REL CONST PUB UNTYP. CODE A96
AppU0 ABS CONST EXT [012] UNTYP. __EXTERNS Solved Extern
BACKSLASH REL CONST PUB UNTYP. CODE 1B70
BASE REL CONST PUB UNTYP. CODE 968
BCSCTL1 ABS CONST UNTYP. ASEG 57
BCSCTL2 ABS CONST UNTYP. ASEG 58
BCSCTL3 ABS CONST UNTYP. ASEG 53
BEGIN REL CONST PUB UNTYP. CODE 169C
BELL REL CONST PUB UNTYP. CODE 1BA8
BIN REL CONST PUB UNTYP. CODE 1BBA
BLANK REL CONST PUB UNTYP. CODE A34
BOOT REL CONST PUB UNTYP. CODE 1A92
BOOTIP REL CONST PUB UNTYP. CODE 1A94
BRACCHAR REL CONST PUB UNTYP. CODE 14A0
BRACTICK REL CONST PUB UNTYP. CODE 160A
BUILDS REL CONST PUB UNTYP. CODE 14F8
CACTL1 ABS CONST UNTYP. ASEG 59
CACTL2 ABS CONST UNTYP. ASEG 5A
CALBC1_12MHZ ABS CONST UNTYP. ASEG 10FB
CALBC1_16MHZ ABS CONST UNTYP. ASEG 10F9
CALBC1_1MHZ ABS CONST UNTYP. ASEG 10FF
CALBC1_8MHZ ABS CONST UNTYP. ASEG 10FD
CALDCO_12MHZ ABS CONST UNTYP. ASEG 10FA
CALDCO_16MHZ ABS CONST UNTYP. ASEG 10F8
CALDCO_1MHZ ABS CONST UNTYP. ASEG 10FE
CALDCO_8MHZ ABS CONST UNTYP. ASEG 10FC
CAPD ABS CONST UNTYP. ASEG 5B
CAPITALIZE REL CONST PUB UNTYP. CODE 11FC
CAPS REL CONST PUB UNTYP. CODE 9E4
CAPS1 REL CONST UNTYP. CODE 1212
CAPS2 REL CONST UNTYP. CODE 1220
CCOMMA REL CONST PUB UNTYP. CODE 1050
CCRC REL CONST PUB UNTYP. CODE 19CC
CELL REL CONST PUB UNTYP. CODE 830
CELLPLUS REL CONST PUB UNTYP. CODE 83E
CELLS REL CONST PUB UNTYP. CODE 84E
CEXIT REL CONST PUB UNTYP. CODE 8F4
CF430FRend REL CONST UNTYP. CODE 1D32
CFETCH REL CONST PUB UNTYP. CODE 22A
CHARPLUS REL CONST PUB UNTYP. CODE 85A
CHARR REL CONST PUB UNTYP. CODE 148A
CHARS REL CONST PUB UNTYP. CODE 866
CMOVE REL CONST PUB UNTYP. CODE 6DC
CMOVEUP REL CONST PUB UNTYP. CODE 700
CMOVE_1 REL CONST UNTYP. CODE 6E6
CMOVE_X REL CONST UNTYP. CODE 6F0
CMOVU_1 REL CONST UNTYP. CODE 70E
CMOVU_X REL CONST UNTYP. CODE 71A
COLD REL CONST PUB UNTYP. CODE 1AF4
COLON REL CONST PUB UNTYP. CODE 15E6
COMMA REL CONST PUB UNTYP. CODE 103A
COMMABRANCH REL CONST PUB UNTYP. CODE 90A
COMMACALL REL CONST PUB UNTYP. CODE 8B0
COMMACF REL CONST PUB UNTYP. CODE 898
COMMADEST REL CONST PUB UNTYP. CODE 918
COMMAJMP REL CONST PUB UNTYP. CODE 8C4
COMMANONE REL CONST PUB UNTYP. CODE 942
COMMAXT REL CONST PUB UNTYP. CODE 880
CONSTANT REL CONST PUB UNTYP. CODE 84
COR REL CONST PUB UNTYP. CODE A7A
CORPOWERON ABS CONST UNTYP. CODE 186
CORREST ABS CONST UNTYP. CODE 18E
COUNT REL CONST PUB UNTYP. CODE CB2
CR REL CONST PUB UNTYP. CODE CC4
CRC REL CONST PUB UNTYP. CODE 19F0
CREATE REL CONST PUB UNTYP. CODE 150E
CSTORE REL CONST PUB UNTYP. CODE 238
DABS REL CONST PUB UNTYP. CODE B10
DCOCTL ABS CONST UNTYP. ASEG 56
DDP REL CONST PUB UNTYP. CODE 980
DECIMAL REL CONST PUB UNTYP. CODE FF2
DEPTH REL CONST PUB UNTYP. CODE 1816
DIGITQ REL CONST PUB UNTYP. CODE 124C
DIV1 REL CONST UNTYP. CODE 68A
DIV2 REL CONST UNTYP. CODE 690
DIV3 REL CONST UNTYP. CODE 6A4
DIV4 REL CONST UNTYP. CODE 6A6
DIVIDE REL CONST UNTYP. CODE 684
DNEG1 REL CONST UNTYP. CODE B06
DNEGATE REL CONST PUB UNTYP. CODE ADE
DO REL CONST PUB UNTYP. CODE 1726
DOALIAS REL CONST PUB UNTYP. CODE C4
DOCODE REL CONST UNTYP. CODE Not solved
DOCOLON REL CONST PUB UNTYP. CODE 5A
DOCON REL CONST PUB UNTYP. CODE 8C
DOES REL CONST PUB UNTYP. CODE 1542
DOROM REL CONST PUB UNTYP. CODE 98
DOT REL CONST PUB UNTYP. CODE FCC
DOTCOLD REL CONST PUB UNTYP. CODE 1ADE
DOTQUOTE REL CONST PUB UNTYP. CODE E94
DOTS REL CONST PUB UNTYP. CODE 198C
DOTS1 REL CONST UNTYP. CODE 19BC
DOTS2 REL CONST UNTYP. CODE 19CA
DOTSTATUS REL CONST PUB UNTYP. CODE 13D4
DOTVER REL CONST PUB UNTYP. CODE 1B84
DOTWOCON REL CONST PUB UNTYP. CODE 1B5A
DOUSER REL CONST PUB UNTYP. CODE B4
DOVAR REL CONST PUB UNTYP. CODE 8C
DROP REL CONST PUB UNTYP. CODE 10A
DTOI REL CONST PUB UNTYP. CODE 36A
DTOI_BYTE REL CONST UNTYP. CODE 39E
DTOI_END REL CONST UNTYP. CODE 3A4
DTOI_LOOP REL CONST UNTYP. CODE 374
DTOI_WORD REL CONST UNTYP. CODE 38C
DTOI_X REL CONST UNTYP. CODE 3B6
DUMP REL CONST PUB UNTYP. CODE 1920
DUP REL CONST PUB UNTYP. CODE E4
ELSS REL CONST PUB UNTYP. CODE 1680
EMIT REL CONST PUB UNTYP. CODE 7AE
EMITLOOP REL CONST UNTYP. CODE 7B0
ENDLOOP REL CONST PUB UNTYP. CODE 1744
ENVIRONMENTQ REL CONST PUB UNTYP. CODE 1834
EQUAL REL CONST PUB UNTYP. CODE 508
EVALUATE REL CONST PUB UNTYP. CODE 13B2
EXECUTE REL CONST PUB UNTYP. CODE 2C
EXIT REL CONST PUB UNTYP. CODE 52
FACTORY REL CONST PUB UNTYP. CODE 1B12
FACTORYIP REL CONST PUB UNTYP. CODE 1B14
FCTL1 ABS CONST UNTYP. ASEG 128
FCTL2 ABS CONST UNTYP. ASEG 12A
FCTL3 ABS CONST UNTYP. ASEG 12C
FETCH REL CONST PUB UNTYP. CODE 20A
FILL REL CONST PUB UNTYP. CODE 6B8
FILL_1 REL CONST UNTYP. CODE 6C2
FILL_X REL CONST UNTYP. CODE 6CC
FIND REL CONST PUB UNTYP. CODE 119C
FIND1 REL CONST UNTYP. CODE 11A2
FIND2 REL CONST UNTYP. CODE 11BA
FIND3 REL CONST UNTYP. CODE 11D8
FLALIGNED REL CONST PUB UNTYP. CODE 1858
FLERASE REL CONST PUB UNTYP. CODE 252
FLE_1 REL CONST UNTYP. CODE 258
FLE_INFO REL CONST UNTYP. CODE 268
FLE_OK REL CONST UNTYP. CODE 274
FLE_X REL CONST UNTYP. CODE 2AC
FL_INFO REL CONST UNTYP. CODE 2A6
FMMOD1 REL CONST UNTYP. CODE B94
FMSLASHMOD REL CONST PUB UNTYP. CODE B6E
FOR REL CONST PUB UNTYP. CODE 17A8
GREATER REL CONST PUB UNTYP. CODE 53E
HEADR REL CONST PUB UNTYP. CODE 14CA
HERE REL CONST PUB UNTYP. CODE 101A
HEX REL CONST PUB UNTYP. CODE 1006
HIDE REL CONST PUB UNTYP. CODE 1596
HOLD REL CONST PUB UNTYP. CODE F0E
HP REL CONST PUB UNTYP. CODE 9A8
IALLOT REL CONST PUB UNTYP. CODE 107C
ICCOMMA REL CONST PUB UNTYP. CODE 10A2
ICFETCH REL CONST PUB UNTYP. CODE 360
ICOMMA REL CONST PUB UNTYP. CODE 108A
ICOUNT REL CONST PUB UNTYP. CODE DCA
ICSTORE REL CONST PUB UNTYP. CODE 30C
ICST_INFO REL CONST UNTYP. CODE 322
ICST_OK REL CONST UNTYP. CODE 32E
ICST_RAM REL CONST UNTYP. CODE 33C
IDP REL CONST PUB UNTYP. CODE 9BE
IE1 ABS CONST UNTYP. ASEG 0
IE2 ABS CONST UNTYP. ASEG 1
IFETCH REL CONST PUB UNTYP. CODE 356
IFF REL CONST PUB UNTYP. CODE 1658
IFG1 ABS CONST UNTYP. ASEG 2
IFG2 ABS CONST UNTYP. ASEG 3
IHERE REL CONST PUB UNTYP. CODE 106A
II REL CONST PUB UNTYP. CODE 5FA
IMMEDIATE REL CONST PUB UNTYP. CODE 15D0
IMMEDQ REL CONST PUB UNTYP. CODE 1184
INFOB REL CONST PUB UNTYP. CODE A88
INTER1 REL CONST UNTYP. CODE 1354
INTER2 REL CONST UNTYP. CODE 137E
INTER3 REL CONST UNTYP. CODE 1380
INTER4 REL CONST UNTYP. CODE 1384
INTER5 REL CONST UNTYP. CODE 1390
INTER6 REL CONST UNTYP. CODE 139E
INTER8 REL CONST UNTYP. CODE 139E
INTER9 REL CONST UNTYP. CODE 13A2
INTERPRET REL CONST PUB UNTYP. CODE 1346
INVERT REL CONST PUB UNTYP. CODE 43C
ISQUOTE REL CONST PUB UNTYP. CODE E50
ISTORE REL CONST PUB UNTYP. CODE 2B8
IST_INFO REL CONST UNTYP. CODE 2D2
IST_OK REL CONST UNTYP. CODE 2DE
IST_RAM REL CONST UNTYP. CODE 2EC
IST_X REL CONST UNTYP. CODE 2FE
ITHERE REL CONST PUB UNTYP. CODE 1A1C
ITOD REL CONST PUB UNTYP. CODE 728
ITYP3 REL CONST UNTYP. CODE DF0
ITYP4 REL CONST UNTYP. CODE DFE
ITYP5 REL CONST UNTYP. CODE E00
ITYPE REL CONST PUB UNTYP. CODE DE0
IWORD REL CONST PUB UNTYP. CODE EAA
IWORD1 REL CONST UNTYP. CODE EAE
IWORDC REL CONST PUB UNTYP. CODE EBC
JJ REL CONST PUB UNTYP. CODE 610
KEY REL CONST PUB UNTYP. CODE 7C8
KEYLOOP REL CONST UNTYP. CODE 7CA
KEYQ REL CONST PUB UNTYP. CODE 7E6
L$002 REL CONST UNTYP. CODE 65A
L$01 REL CONST UNTYP. CODE 662
L0 REL CONST PUB UNTYP. CODE 9FA
LATEST REL CONST PUB UNTYP. CODE 99E
LDUMP1 REL CONST UNTYP. CODE 192A
LDUMP2 REL CONST UNTYP. CODE 1944
LDUMP3 REL CONST UNTYP. CODE 1962
LEAV REL CONST PUB UNTYP. CODE 178A
LEFTBRACKET REL CONST PUB UNTYP. CODE 1570
LESS REL CONST PUB UNTYP. CODE 52A
LESSNUM REL CONST PUB UNTYP. CODE F26
LFROM REL CONST PUB UNTYP. CODE 170E
LITER1 REL CONST UNTYP. CODE 1240
LITERAL REL CONST PUB UNTYP. CODE 122E
LOO REL CONST PUB UNTYP. CODE 1762
LOOP1 REL CONST UNTYP. CODE 174A
LOOP2 REL CONST UNTYP. CODE 1758
LP REL CONST PUB UNTYP. CODE 9B2
LSHIFT REL CONST PUB UNTYP. CODE 4A8
LSH_1 REL CONST UNTYP. CODE 4B2
LSH_X REL CONST UNTYP. CODE 4B8
LSTACK ABS CONST EXT [003] UNTYP. __EXTERNS Solved Extern
MACU REL CONST UNTYP. CODE 656
MARKER REL CONST PUB UNTYP. CODE 1876
MAX REL CONST PUB UNTYP. CODE C06
MAX1 REL CONST UNTYP. CODE C12
MEM REL CONST PUB UNTYP. CODE 1CB6
MEMBOT REL CONST PUB UNTYP. CODE 1C9C
MEMTOP REL CONST PUB UNTYP. CODE 1CAA
MIN REL CONST PUB UNTYP. CODE C1E
MIN1 REL CONST UNTYP. CODE C2A
MINUS REL CONST PUB UNTYP. CODE 3F8
MODD REL CONST PUB UNTYP. CODE BD2
MOVE REL CONST PUB UNTYP. CODE 17EA
MOVE1 REL CONST UNTYP. CODE 1806
MOVE2 REL CONST UNTYP. CODE 180A
MPLUS REL CONST PUB UNTYP. CODE 3E2
MPYU REL CONST UNTYP. CODE 652
MS REL CONST PUB UNTYP. CODE 1BF4
MSTAR REL CONST PUB UNTYP. CODE B1E
NEGATE REL CONST PUB UNTYP. CODE 44E
NEQUAL REL CONST PUB UNTYP. CODE 7A4
NEWEST REL CONST PUB UNTYP. CODE 9CC
NEXTT REL CONST PUB UNTYP. CODE 17BC
NFATOCFA REL CONST PUB UNTYP. CODE 116A
NFATOLFA REL CONST PUB UNTYP. CODE 1154
NINIT REL CONST PUB UNTYP. CODE A6E
NIP REL CONST PUB UNTYP. CODE 164
NODUP REL CONST UNTYP. CODE FE
NOOP REL CONST PUB UNTYP. CODE 1846
NOTEQUAL REL CONST PUB UNTYP. CODE 51C
NUM REL CONST PUB UNTYP. CODE F5A
NUMGREATER REL CONST PUB UNTYP. CODE F86
NUMS REL CONST PUB UNTYP. CODE F70
NUMS1 REL CONST UNTYP. CODE F72
ONEMINUS REL CONST PUB UNTYP. CODE 46C
ONEMS REL CONST PUB UNTYP. CODE 1BCE
ONEPLUS REL CONST PUB UNTYP. CODE 45E
ORR REL CONST PUB UNTYP. CODE 41A
OVER REL CONST PUB UNTYP. CODE 130
P1 REL CONST PUB UNTYP. CODE 1CDE
P1DIR ABS CONST UNTYP. ASEG 22
P1IE ABS CONST UNTYP. ASEG 25
P1IES ABS CONST UNTYP. ASEG 24
P1IFG ABS CONST UNTYP. ASEG 23
P1IN ABS CONST UNTYP. ASEG 20
P1OUT ABS CONST UNTYP. ASEG 21
P1REN ABS CONST UNTYP. ASEG 27
P1SEL ABS CONST UNTYP. ASEG 26
P1SEL2 ABS CONST UNTYP. ASEG 41
P2 REL CONST PUB UNTYP. CODE 1CE8
P2DIR ABS CONST UNTYP. ASEG 2A
P2IE ABS CONST UNTYP. ASEG 2D
P2IES ABS CONST UNTYP. ASEG 2C
P2IFG ABS CONST UNTYP. ASEG 2B
P2IN ABS CONST UNTYP. ASEG 28
P2OUT ABS CONST UNTYP. ASEG 29
P2REN ABS CONST UNTYP. ASEG 2F
P2SEL ABS CONST UNTYP. ASEG 2E
P2SEL2 ABS CONST UNTYP. ASEG 42
P3 REL CONST PUB UNTYP. CODE 1CF2
P3DIR ABS CONST UNTYP. ASEG 1A
P3IN ABS CONST UNTYP. ASEG 18
P3OUT ABS CONST UNTYP. ASEG 19
P3REN ABS CONST UNTYP. ASEG 10
P3SEL ABS CONST UNTYP. ASEG 1B
P3SEL2 ABS CONST UNTYP. ASEG 43
PAD REL CONST PUB UNTYP. CODE 9F0
PADAREA ABS CONST EXT [002] UNTYP. __EXTERNS Solved Extern
PAREN REL CONST PUB UNTYP. CODE 14B4
PLUS REL CONST PUB UNTYP. CODE 3C2
PLUSLOOP REL CONST PUB UNTYP. CODE 1776
PLUSSTORE REL CONST PUB UNTYP. CODE 3D0
POST1 REL CONST UNTYP. CODE 164E
POST2 REL CONST UNTYP. CODE 1650
POSTPONE REL CONST PUB UNTYP. CODE 1624
PROMPT REL CONST PUB UNTYP. CODE 13E0
PROMPT1 REL CONST UNTYP. CODE 13F4
PSTACK ABS CONST EXT [004] UNTYP. __EXTERNS Solved Extern
PUSHTOS REL CONST UNTYP. CODE E6
QABO1 REL CONST UNTYP. CODE 144E
QABORT REL CONST PUB UNTYP. CODE 1442
QDNEGATE REL CONST PUB UNTYP. CODE AFC
QDUP REL CONST PUB UNTYP. CODE F8
QNEG1 REL CONST UNTYP. CODE AC0
QNEGATE REL CONST PUB UNTYP. CODE AB6
QNUM1 REL CONST UNTYP. CODE 1326
QNUM2 REL CONST UNTYP. CODE 1332
QNUM3 REL CONST UNTYP. CODE 1336
QNUMBER REL CONST PUB UNTYP. CODE 1300
QSIGN REL CONST PUB UNTYP. CODE 1288
QSIGN1 REL CONST UNTYP. CODE 12B2
QUIT REL CONST PUB UNTYP. CODE 13FE
QUIT1 REL CONST UNTYP. CODE 1412
QUITIP REL CONST PUB UNTYP. CODE 1400
RAMDICT ABS CONST EXT [007] UNTYP. __EXTERNS Solved Extern
RECURSE REL CONST PUB UNTYP. CODE 155E
REPEAT REL CONST PUB UNTYP. CODE 16EA
REVEAL REL CONST PUB UNTYP. CODE 15B6
RFETCH REL CONST PUB UNTYP. CODE 196
RFROM REL CONST PUB UNTYP. CODE 182
RIGHTBRACKET REL CONST PUB UNTYP. CODE 1582
ROMDICT ABS CONST EXT [-001] UNTYP. __EXTERNS Solved Extern
ROT REL CONST PUB UNTYP. CODE 148
RPFETCH REL CONST PUB UNTYP. CODE 1D4
RPSTORE REL CONST PUB UNTYP. CODE 1EA
RSHIFT REL CONST PUB UNTYP. CODE 4C8
RSH_1 REL CONST UNTYP. CODE 4D2
RSH_X REL CONST UNTYP. CODE 4DA
RSTACK ABS CONST EXT [005] UNTYP. __EXTERNS Solved Extern
RZERO REL CONST PUB UNTYP. CODE A04
S0 REL CONST PUB UNTYP. CODE A0E
S2 REL CONST PUB UNTYP. CODE 1D1A
SAVE REL CONST PUB UNTYP. CODE 1A6E
SCAN REL CONST PUB UNTYP. CODE 758
SCAN_1 REL CONST UNTYP. CODE 762
SCAN_X REL CONST UNTYP. CODE 76C
SEMICOLON REL CONST PUB UNTYP. CODE 15F8
SEQUAL REL CONST PUB UNTYP. CODE 77C
SEQU_1 REL CONST UNTYP. CODE 786
SEQU_X REL CONST UNTYP. CODE 79A
SIGN REL CONST PUB UNTYP. CODE F9E
SIGN1 REL CONST UNTYP. CODE FAC
SKIP REL CONST PUB UNTYP. CODE 732
SKIP_1 REL CONST UNTYP. CODE 73C
SKIP_X REL CONST UNTYP. CODE 746
SLASH REL CONST PUB UNTYP. CODE BC2
SLASHMOD REL CONST PUB UNTYP. CODE BB0
SLASHSTRING REL CONST PUB UNTYP. CODE 10D0
SMISMATCH REL CONST UNTYP. CODE 794
SMSLASHREM REL CONST PUB UNTYP. CODE B40
SOURCE REL CONST PUB UNTYP. CODE 10BC
SPACE REL CONST PUB UNTYP. CODE CDE
SPACES REL CONST PUB UNTYP. CODE CF0
SPCS1 REL CONST UNTYP. CODE CF2
SPCS2 REL CONST UNTYP. CODE D00
SPFETCH REL CONST PUB UNTYP. CODE 1AC
SPSTORE REL CONST PUB UNTYP. CODE 1C2
SQEST REL CONST PUB UNTYP. CODE 1D28
SQUOTE REL CONST PUB UNTYP. CODE E6E
SSMOD REL CONST PUB UNTYP. CODE BE4
STAR REL CONST PUB UNTYP. CODE BA0
STARSLASH REL CONST PUB UNTYP. CODE BF6
STATE REL CONST PUB UNTYP. CODE 976
STOD REL CONST PUB UNTYP. CODE AA2
STORCOLON REL CONST PUB UNTYP. CODE 8DA
STORE REL CONST PUB UNTYP. CODE 218
STORECF REL CONST PUB UNTYP. CODE 88C
STOREDEST REL CONST PUB UNTYP. CODE 92C
SWAP REL CONST PUB UNTYP. CODE 11A
SWAPBYTES REL CONST PUB UNTYP. CODE 47A
TA0CCR0 ABS CONST UNTYP. ASEG 172
TA0CCR1 ABS CONST UNTYP. ASEG 174
TA0CCR2 ABS CONST UNTYP. ASEG 176
TA0CCTL0 ABS CONST UNTYP. ASEG 162
TA0CCTL1 ABS CONST UNTYP. ASEG 164
TA0CCTL2 ABS CONST UNTYP. ASEG 166
TA0CTL ABS CONST UNTYP. ASEG 160
TA0IV ABS CONST UNTYP. ASEG 12E
TA0R ABS CONST UNTYP. ASEG 170
TA1CCR0 ABS CONST UNTYP. ASEG 192
TA1CCR1 ABS CONST UNTYP. ASEG 194
TA1CCR2 ABS CONST UNTYP. ASEG 196
TA1CCTL0 ABS CONST UNTYP. ASEG 182
TA1CCTL1 ABS CONST UNTYP. ASEG 184
TA1CCTL2 ABS CONST UNTYP. ASEG 186
TA1CTL ABS CONST UNTYP. ASEG 180
TA1IV ABS CONST UNTYP. ASEG 11E
TA1R ABS CONST UNTYP. ASEG 190
THEN REL CONST PUB UNTYP. CODE 166E
TIB REL CONST PUB UNTYP. CODE A1A
TIBAREA ABS CONST EXT [006] UNTYP. __EXTERNS Solved Extern
TIBSIZE REL CONST PUB UNTYP. CODE A2A
TIB_SIZE ABS CONST EXT [008] UNTYP. __EXTERNS Solved Extern
TICK REL CONST PUB UNTYP. CODE 146E
TICKSOURCE REL CONST PUB UNTYP. CODE 990
TOBODY REL CONST PUB UNTYP. CODE 872
TOCOUNTED REL CONST PUB UNTYP. CODE 10EC
TODIGIT REL CONST PUB UNTYP. CODE F3A
TOIN REL CONST PUB UNTYP. CODE 95C
TOL REL CONST PUB UNTYP. CODE 16F8
TONUM1 REL CONST UNTYP. CODE 12C2
TONUM2 REL CONST UNTYP. CODE 12D8
TONUM3 REL CONST UNTYP. CODE 12F2
TONUMBER REL CONST PUB UNTYP. CODE 12C0
TOR REL CONST PUB UNTYP. CODE 172
TOSFALSE REL CONST UNTYP. CODE 510
TOSTRUE REL CONST UNTYP. CODE 532
TUCK REL CONST PUB UNTYP. CODE 1FC
TWOCONSTANT REL CONST PUB UNTYP. CODE 1B50
TWODROP REL CONST PUB UNTYP. CODE C60
TWODUP REL CONST PUB UNTYP. CODE C70
TWOFETCH REL CONST PUB UNTYP. CODE C34
TWOOVER REL CONST PUB UNTYP. CODE C98
TWOSLASH REL CONST PUB UNTYP. CODE 496
TWOSTAR REL CONST PUB UNTYP. CODE 488
TWOSTORE REL CONST PUB UNTYP. CODE C48
TWOSWAP REL CONST PUB UNTYP. CODE C82
TYP REL CONST PUB UNTYP. CODE D9E
TYP3 REL CONST UNTYP. CODE DAE
TYP4 REL CONST UNTYP. CODE DBC
TYP5 REL CONST UNTYP. CODE DBE
U0 REL CONST PUB UNTYP. CODE 950
UAREA ABS CONST EXT [001] UNTYP. __EXTERNS Solved Extern
UAREA_SIZE ABS CONST EXT [009] UNTYP. __EXTERNS Solved Extern
UCA0ABCTL ABS CONST UNTYP. ASEG 5D
UCA0BR0 ABS CONST UNTYP. ASEG 62
UCA0BR1 ABS CONST UNTYP. ASEG 63
UCA0CTL0 ABS CONST UNTYP. ASEG 60
UCA0CTL1 ABS CONST UNTYP. ASEG 61
UCA0IRRCTL ABS CONST UNTYP. ASEG 5F
UCA0IRTCTL ABS CONST UNTYP. ASEG 5E
UCA0MCTL ABS CONST UNTYP. ASEG 64
UCA0RXBUF ABS CONST UNTYP. ASEG 66
UCA0STAT ABS CONST UNTYP. ASEG 65
UCA0TXBUF ABS CONST UNTYP. ASEG 67
UCB0BR0 ABS CONST UNTYP. ASEG 6A
UCB0BR1 ABS CONST UNTYP. ASEG 6B
UCB0CTL0 ABS CONST UNTYP. ASEG 68
UCB0CTL1 ABS CONST UNTYP. ASEG 69
UCB0I2CIE ABS CONST UNTYP. ASEG 6C
UCB0I2COA ABS CONST UNTYP. ASEG 118
UCB0I2CSA ABS CONST UNTYP. ASEG 11A
UCB0RXBUF ABS CONST UNTYP. ASEG 6E
UCB0STAT ABS CONST UNTYP. ASEG 6D
UCB0TXBUF ABS CONST UNTYP. ASEG 6F
UDOT REL CONST PUB UNTYP. CODE FB4
UDOTR REL CONST PUB UNTYP. CODE 18F8
UDSLASHMOD REL CONST PUB UNTYP. CODE ED0
UDSTAR REL CONST PUB UNTYP. CODE EF0
UGREATER REL CONST PUB UNTYP. CODE 55C
UINIT REL CONST PUB UNTYP. CODE A42
ULESS REL CONST PUB UNTYP. CODE 54C
UMAX REL CONST PUB UNTYP. CODE D24
UMAX1 REL CONST UNTYP. CODE D30
UMIN REL CONST PUB UNTYP. CODE D0C
UMIN1 REL CONST UNTYP. CODE D18
UMSLASHMOD REL CONST PUB UNTYP. CODE 67E
UMSTAR REL CONST PUB UNTYP. CODE 64E
UNLOOP REL CONST PUB UNTYP. CODE 62C
UNTIL REL CONST PUB UNTYP. CODE 16AC
UNUSED REL CONST PUB UNTYP. CODE 1CCC
UP ABS CONST EXT [000] UNTYP. __EXTERNS Solved Extern
UPC REL CONST PUB UNTYP. CODE 11DA
UPC1 REL CONST UNTYP. CODE 11F4
USER REL CONST PUB UNTYP. CODE AC
VALIDQ REL CONST PUB UNTYP. CODE 1A58
VARIABLE REL CONST PUB UNTYP. CODE 6E
WARM REL CONST PUB UNTYP. CODE 1AD0
WDS1 REL CONST UNTYP. CODE 18D2
WDTCTL ABS CONST UNTYP. ASEG 120
WHILE REL CONST PUB UNTYP. CODE 16D8
WIPE REL CONST PUB UNTYP. CODE 1B28
WITHIN REL CONST PUB UNTYP. CODE 17D2
WORD1 REL CONST UNTYP. CODE 1126
WORDD REL CONST PUB UNTYP. CODE 1102
WORDS REL CONST PUB UNTYP. CODE 18CC
XDOES REL CONST PUB UNTYP. CODE 152A
XISQUOTE REL CONST PUB UNTYP. CODE E0C
XORR REL CONST PUB UNTYP. CODE 42A
XSQUOTE REL CONST PUB UNTYP. CODE E24
ZEROEQUAL REL CONST PUB UNTYP. CODE 4E6
ZEROLESS REL CONST PUB UNTYP. CODE 4F6
__MSP430G2203__ ABS CONST UNTYP. ASEG Not solved
boot1 REL CONST UNTYP. CODE 1AC6
bran REL CONST PUB UNTYP. CODE 56E
cclr REL CONST PUB UNTYP. CODE 1C4E
ccrc1 REL CONST UNTYP. CODE 19D8
ccrc2 REL CONST UNTYP. CODE 19E0
cget REL CONST PUB UNTYP. CODE 1C7E
cget1 REL CONST UNTYP. CODE 1C8A
cget2 REL CONST UNTYP. CODE 1C8C
cor ABS CONST EXT [010] UNTYP. __EXTERNS Solved Extern
crcval ABS CONST EXT [013] UNTYP. __EXTERNS Solved Extern
cset REL CONST PUB UNTYP. CODE 1C22
ctoggle REL CONST PUB UNTYP. CODE 1C68
dobran REL CONST UNTYP. CODE 570
docreate REL CONST PUB UNTYP. CODE 8C
dodoes REL CONST PUB UNTYP. CODE C8
donext REL CONST UNTYP. CODE 7DA
donoop REL CONST UNTYP. CODE 7DA
dotcold0 REL CONST UNTYP. CODE 1AE3
dotcold1 REL CONST UNTYP. CODE 1AE8
green REL CONST PUB UNTYP. CODE 1D0E
ih1 REL CONST UNTYP. CODE 1A20
infoB ABS CONST EXT [011] UNTYP. __EXTERNS Solved Extern
invalid REL CONST UNTYP. CODE 1AA6
lastword REL CONST PUB UNTYP. CODE 1D23
link REL VAR UNTYP. CODE 1D23
lit REL CONST PUB UNTYP. CODE 3C
ms1 REL CONST UNTYP. CODE 1BFC
nullirq ABS CONST EXT [-001] UNTYP. __EXTERNS Solved Extern
onems1 REL CONST UNTYP. CODE 1BDA
onems2 REL CONST UNTYP. CODE 1BE4
pcrc1 REL CONST UNTYP. CODE 1A00
pcrc2 REL CONST UNTYP. CODE 1A0E
pcrc3 REL CONST UNTYP. CODE 1A10
qbran REL CONST PUB UNTYP. CODE 582
red REL CONST PUB UNTYP. CODE 1CFE
reset REL CONST UNTYP. CODE 1AB4
valid REL CONST UNTYP. CODE 1AA4
ver0 REL CONST UNTYP. CODE 1
verend REL CONST UNTYP. CODE 20
version REL CONST UNTYP. CODE 0
warm0 REL CONST UNTYP. CODE 1AD5
warm1 REL CONST UNTYP. CODE 1ADA
wclr REL CONST PUB UNTYP. CODE 1C38
wipmsg0 REL CONST UNTYP. CODE 1B2D
wipmsg1 REL CONST UNTYP. CODE 1B34
wset REL CONST PUB UNTYP. CODE 1C0C
xdo REL CONST PUB UNTYP. CODE 598
xloop REL CONST PUB UNTYP. CODE 5BE
xnext REL CONST PUB UNTYP. CODE 636
xplusloop REL CONST PUB UNTYP. CODE 5DE
##############################
# CRC:34AC #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 7474 #
##############################